| Message ID | 7237fa9e-4d3a-8a82-10c6-76737c23ed6f@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi Vignesh, I tried this patch on an Arria10 SOCFPGA devkit against the 4.1.33-ltsi kernel, and it did not go well. Commands to the flash chip timedout resulting in the probe function failing. I ran into other problems, not related to cadence-quadspi, that prevented me from testing against 4.9 and 4.12 kernels, but I suspect similar behavior. Matthew Gerlach On Wed, 27 Sep 2017, Vignesh R wrote: > Hi Matthew, > > On Tuesday 26 September 2017 05:19 AM, Marek Vasut wrote: > [...] >>>>> Ok thanks! Do you know if pm_runtime_get_sync() can enable clocks for >>>>> QSPI on SoCFPGA or if clk_prepare_enable() is needed? Just trying to see >>>>> if its possible to get rid of clk_*() calls in favor of pm_*() calls. >>>> >>>> Not of the top of my head, sorry. +CC Matthew, he should know. >>> >>> I am not an expert at the clock framework nor the power management, but I >>> did ask around a bit. No one I asked was planning to change the clk_*() >>> calls to pm_*() call, but the feedback was that it would be a good idea. >> >> The question is, if we do the replacement, will it break on socfpga ? >> A quick test might be useful. >> > > yes, a quick qspi test with clk_prepare_enable() replaced by pm_*() calls > like below patch would be helpful: > > > diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c > index 53c7d8e0327a..7ad3e176cc88 100644 > --- a/drivers/mtd/spi-nor/cadence-quadspi.c > +++ b/drivers/mtd/spi-nor/cadence-quadspi.c > @@ -34,6 +34,7 @@ > #include <linux/sched.h> > #include <linux/spi/spi.h> > #include <linux/timer.h> > +#include <linux/pm_runtime.h> > > #define CQSPI_NAME "cadence-qspi" > #define CQSPI_MAX_CHIPSELECT 16 > @@ -1206,11 +1207,8 @@ static int cqspi_probe(struct platform_device *pdev) > return -ENXIO; > } > > - ret = clk_prepare_enable(cqspi->clk); > - if (ret) { > - dev_err(dev, "Cannot enable QSPI clock.\n"); > - return ret; > - } > + pm_runtime_enable(dev); > + pm_runtime_get_sync(dev); > > cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); > > > > > > -- > Regards > Vignesh >
Hi, On 9/28/2017 8:31 PM, matthew.gerlach@linux.intel.com wrote: > > Hi Vignesh, > > I tried this patch on an Arria10 SOCFPGA devkit against the 4.1.33-ltsi > kernel, and it did not go well. Commands to the flash chip timedout > resulting in the probe function failing. I ran into other problems, not > related to cadence-quadspi, that prevented me from testing against 4.9 and > 4.12 kernels, but I suspect similar behavior. > Ok, thanks! I will keep the clk_*() calls for now. Regards Vignesh > Matthew Gerlach > > On Wed, 27 Sep 2017, Vignesh R wrote: > >> Hi Matthew, >> >> On Tuesday 26 September 2017 05:19 AM, Marek Vasut wrote: >> [...] >>>>>> Ok thanks! Do you know if pm_runtime_get_sync() can enable clocks for >>>>>> QSPI on SoCFPGA or if clk_prepare_enable() is needed? Just trying to see >>>>>> if its possible to get rid of clk_*() calls in favor of pm_*() calls. >>>>> >>>>> Not of the top of my head, sorry. +CC Matthew, he should know. >>>> >>>> I am not an expert at the clock framework nor the power management, but I >>>> did ask around a bit. No one I asked was planning to change the clk_*() >>>> calls to pm_*() call, but the feedback was that it would be a good idea. >>> >>> The question is, if we do the replacement, will it break on socfpga ? >>> A quick test might be useful. >>> >> >> yes, a quick qspi test with clk_prepare_enable() replaced by pm_*() calls >> like below patch would be helpful: >> >> >> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c >> index 53c7d8e0327a..7ad3e176cc88 100644 >> --- a/drivers/mtd/spi-nor/cadence-quadspi.c >> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c >> @@ -34,6 +34,7 @@ >> #include <linux/sched.h> >> #include <linux/spi/spi.h> >> #include <linux/timer.h> >> +#include <linux/pm_runtime.h> >> >> #define CQSPI_NAME "cadence-qspi" >> #define CQSPI_MAX_CHIPSELECT 16 >> @@ -1206,11 +1207,8 @@ static int cqspi_probe(struct platform_device *pdev) >> return -ENXIO; >> } >> >> - ret = clk_prepare_enable(cqspi->clk); >> - if (ret) { >> - dev_err(dev, "Cannot enable QSPI clock.\n"); >> - return ret; >> - } >> + pm_runtime_enable(dev); >> + pm_runtime_get_sync(dev); >> >> cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); >> >> >> >> >> >> -- >> Regards >> Vignesh >> >
diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c index 53c7d8e0327a..7ad3e176cc88 100644 --- a/drivers/mtd/spi-nor/cadence-quadspi.c +++ b/drivers/mtd/spi-nor/cadence-quadspi.c @@ -34,6 +34,7 @@ #include <linux/sched.h> #include <linux/spi/spi.h> #include <linux/timer.h> +#include <linux/pm_runtime.h> #define CQSPI_NAME "cadence-qspi" #define CQSPI_MAX_CHIPSELECT 16 @@ -1206,11 +1207,8 @@ static int cqspi_probe(struct platform_device *pdev) return -ENXIO; } - ret = clk_prepare_enable(cqspi->clk); - if (ret) { - dev_err(dev, "Cannot enable QSPI clock.\n"); - return ret; - } + pm_runtime_enable(dev); + pm_runtime_get_sync(dev); cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);