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Wed, 27 Sep 2017 05:48:32 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Wed, 27 Sep 2017 05:48:32 -0500 Received: from [172.24.190.89] (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8RAmTn6029842; Wed, 27 Sep 2017 05:48:29 -0500 Subject: Re: [PATCH v3 5/5] mtd: spi-nor: cadence-quadspi: Add runtime PM support To: References: <20170924105924.23923-1-vigneshr@ti.com> <20170924105924.23923-6-vigneshr@ti.com> <3a1160f9-a0ae-c84c-d209-af97c3c3b0f6@gmail.com> <4ee69ea4-14cc-4305-bf3f-8fe76d43bf6b@ti.com> <038919d3-ff32-d0a7-4c0a-3be16436052d@ti.com> From: Vignesh R Message-ID: <7237fa9e-4d3a-8a82-10c6-76737c23ed6f@ti.com> Date: Wed, 27 Sep 2017 16:18:49 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.3.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Boris Brezillon , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Marek Vasut , Rob Herring , linux-mtd@lists.infradead.org, Cyrille Pitchen , Brian Norris , David Woodhouse , linux-arm-kernel Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Hi Matthew, On Tuesday 26 September 2017 05:19 AM, Marek Vasut wrote: [...] >>>> Ok thanks! Do you know if pm_runtime_get_sync() can enable clocks for >>>> QSPI on SoCFPGA or if clk_prepare_enable() is needed? Just trying to see >>>> if its possible to get rid of clk_*() calls in favor of pm_*() calls. >>> >>> Not of the top of my head, sorry. +CC Matthew, he should know. >> >> I am not an expert at the clock framework nor the power management, but I >> did ask around a bit.  No one I asked was planning to change the clk_*() >> calls to pm_*() call, but the feedback was that it would be a good idea. > > The question is, if we do the replacement, will it break on socfpga ? > A quick test might be useful. > yes, a quick qspi test with clk_prepare_enable() replaced by pm_*() calls like below patch would be helpful: diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c index 53c7d8e0327a..7ad3e176cc88 100644 --- a/drivers/mtd/spi-nor/cadence-quadspi.c +++ b/drivers/mtd/spi-nor/cadence-quadspi.c @@ -34,6 +34,7 @@ #include #include #include +#include #define CQSPI_NAME "cadence-qspi" #define CQSPI_MAX_CHIPSELECT 16 @@ -1206,11 +1207,8 @@ static int cqspi_probe(struct platform_device *pdev) return -ENXIO; } - ret = clk_prepare_enable(cqspi->clk); - if (ret) { - dev_err(dev, "Cannot enable QSPI clock.\n"); - return ret; - } + pm_runtime_enable(dev); + pm_runtime_get_sync(dev); cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);