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Fri, 8 Nov 2024 21:49:00 -0800 From: Nicolin Chen To: , , , CC: , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH RFCv1 4/7] PCI/MSI: Allow __pci_enable_msi_range to pass in iova Date: Fri, 8 Nov 2024 21:48:49 -0800 Message-ID: <7406707cbcf225fe8f6ec3ce497bdcfc51f27afb.1731130093.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A104:EE_|DS7PR12MB8372:EE_ X-MS-Office365-Filtering-Correlation-Id: 1a22acb9-c352-4df2-63ca-08dd00823ac0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|7416014|376014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: +BxGLQyfguj1Hwk2IQFxNgNS/8XzZOQ0d+YklEHOPj3HusDo+AS++Y5mFjwOpyLLdRrae+JaLcyXACFQ6iskc/sRbSAdyk/m/Due9m5ohc2RuFDlqKX+pcEEDlCertcX+HZGQIWh5jjFmZzufR9OsscyWRyLCXKacHSrwENe1ckFg0rvYLpc83H2VHL94/Eeyku7WfQjif0rMmzOxKIiAzvHid9MwX8BUj8yhiqWM77XO+g85okVLHe+lekTzXAHjS55p/1OdxFH6sa2TOGoUfAJa/gMWBP/w8M8JhfmPnUf59LPAFnxNGnOCw3HhMwOowyjfs298jbIJH/cNV8AEF9iLyFUow0d9HQxLXqN1ecZjESTpvcHf5qQQ6mMNAOsk7rLYT1kHMcBWruvtr4QEM4flgSYYCk65KlX8/Ri5R3KpoFFOrQQVdhGao5ktboGbOljvG+vvwgiACL/NxREwNrX7CnsjPb5ddGR9l8vY8DHMn4jr3dQZ+KJU1YWs2ttZYs/3/NuU7Bhsj97ShziyaHlWjaHTBtV+bZ0upYeO7kieYAI+YsFoAAqyR9ZNeU5c4jxOYpKzBsGYXSwb+QdC+BrReodGVJURiYqX6Qxj0L7e9c2PtLwtzexJRHlw2/j+CSfZKI7flGg4sBg96HwLsYIKZkkNdVjI64IuruIt0D2Eln3UhvdWunAzVamzXvf8bBdcm9hnavshGoz+CeReF6R5Vb8iR8bWjxgJl5lcGj7CeNIj3BVPmr7rG7VP+JhF0Jz0LkVFqy+DLUG2wzXyXNdqPJw0T6eAz1R089QYfzXXEtHR2JdC3NKzAj0Nsaqfo3FropJx3yPQW0aUWEMTVHV+sWc1sYsa6lWMve2LbBgjVG8OnvzPVqU25M9Wpgj4aNH7BNx11onfur+vErH515y6IoS0QBXHj6GQglpnrWFbV6n6HuQZiulQyERShX+EFYKVFqhWm0x8fDJRHRKCLMXIv6HUWRJUpUMOCPlUqDzbe2+PB/X7C/ULIZkQmEE42iNcQ6GU1X0CbhQ6pvxcj1BHtcgRsMPSxqno497m+ku82cz6v5EFucZlfy0bsPu9FnTzt4Tivka7A9fcvHVdnRRdl+1+W5+YnjUkBUGwfJP0IN46gmfoCRDDIwU60uGg6/4Pi3bC6b87yBRLUqhERR6lNMibgBtTzhi8GkXM5G1vTWhgRTJMFir1t0RNl8++8nYuXUAWEibuUh/V6FRIyrZy45axEgvxR3y+M4FFAN+7crVnVnZjhq/6E/U4VasL+NOEMIw5l0VMclHvRH9xYjZOHdSid9PiAMwlFIEb99aYH5/zvmykFMBwTTdRa9TVJPO04WztyF4+367bcOhk78+TvNKJcAf6i1EH8OWm8OR5iGy1y5+Ys2Eal1jEMDdkgNYWBsP8hYayV/nf/lZvw== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(7416014)(376014)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2024 05:49:08.6351 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1a22acb9-c352-4df2-63ca-08dd00823ac0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A104.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB8372 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241108_214918_556520_5B343968 X-CRM114-Status: GOOD ( 12.70 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The previous patch passes in the msi_iova to msi_capability_init, so this allows its caller to do the same. Signed-off-by: Nicolin Chen --- drivers/pci/msi/msi.h | 3 ++- drivers/pci/msi/api.c | 6 ++++-- drivers/pci/msi/msi.c | 4 ++-- 3 files changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/pci/msi/msi.h b/drivers/pci/msi/msi.h index ee53cf079f4e..8009d69bf9a5 100644 --- a/drivers/pci/msi/msi.h +++ b/drivers/pci/msi/msi.h @@ -93,7 +93,8 @@ extern int pci_msi_enable; void pci_msi_shutdown(struct pci_dev *dev); void pci_msix_shutdown(struct pci_dev *dev); void pci_free_msi_irqs(struct pci_dev *dev); -int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec, struct irq_affinity *affd); +int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec, + struct irq_affinity *affd, dma_addr_t iova); int __pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, int minvec, int maxvec, struct irq_affinity *affd, int flags); void __pci_restore_msi_state(struct pci_dev *dev); diff --git a/drivers/pci/msi/api.c b/drivers/pci/msi/api.c index b956ce591f96..99ade7f69cd4 100644 --- a/drivers/pci/msi/api.c +++ b/drivers/pci/msi/api.c @@ -29,7 +29,8 @@ */ int pci_enable_msi(struct pci_dev *dev) { - int rc = __pci_enable_msi_range(dev, 1, 1, NULL); + int rc = __pci_enable_msi_range(dev, 1, 1, NULL, + PHYS_ADDR_MAX); if (rc < 0) return rc; return 0; @@ -274,7 +275,8 @@ int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, } if (flags & PCI_IRQ_MSI) { - nvecs = __pci_enable_msi_range(dev, min_vecs, max_vecs, affd); + nvecs = __pci_enable_msi_range(dev, min_vecs, max_vecs, + affd, PHYS_ADDR_MAX); if (nvecs > 0) return nvecs; } diff --git a/drivers/pci/msi/msi.c b/drivers/pci/msi/msi.c index 95caa81d3421..25da0435c674 100644 --- a/drivers/pci/msi/msi.c +++ b/drivers/pci/msi/msi.c @@ -417,7 +417,7 @@ static int msi_capability_init(struct pci_dev *dev, int nvec, } int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec, - struct irq_affinity *affd) + struct irq_affinity *affd, dma_addr_t iova) { int nvec; int rc; @@ -460,7 +460,7 @@ int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec, return -ENOSPC; } - rc = msi_capability_init(dev, nvec, affd, PHYS_ADDR_MAX); + rc = msi_capability_init(dev, nvec, affd, iova); if (rc == 0) return nvec;