From patchwork Thu Sep 28 11:45:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Schiffer X-Patchwork-Id: 13402859 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6430BE732C5 for ; Thu, 28 Sep 2023 11:46:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Cy+vJzTBsM6FxyQANIdLL3d19/1cfiyCHd3b+MDzEvs=; b=vsLI3OoeNmUnfh EF7EsO3U4m0P7LltZVGH7S0SMz1ARzTrQ4aJWNlPy9GCSgfCnbN6lp26r8biK+N6Tdd94dNCPpBKc qXfXeYsiBfuljeONARPqxl8v4eKtlu17E4hkVI0KPW9y2M9RyVnGzeceNR7rIHFWZw5B4HgFPTYR6 Aw1iisOszU7RGJCnbgb8Ki/UCfDx83m0WEDdZWS3sLb0PjMOSS1NTpLVg8yOh62UiB4KIHmrbU5cX bjpUrY9OBTvf6KdnKpFUhX4hbaEHTK6Uy0DpzZSJzuPVdQUsuhNnp9bTGO3VpQ98mK2czofQ78QEv pK+kN6J3MKbsSwfMx82Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qlpSm-003MKR-0T; Thu, 28 Sep 2023 11:45:48 +0000 Received: from mx1.tq-group.com ([93.104.207.81]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qlpSc-003M89-2n for linux-arm-kernel@lists.infradead.org; Thu, 28 Sep 2023 11:45:40 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1695901538; x=1727437538; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EnjcF8thYe5kjKLOpP9xHh/GIEKF/HW45uCb1c/GqF0=; b=a2PLkhtbWEkSyST8//Qz6rE9jf/MU67LBDF9j+33GuZScnGFbNEcfu7Q UfeZrovEUtf0UNLauDZStVX1QbJtKBiiPDYsFl4WpBdRLSqhiLzHQfdsh BstvsetESBjKgbiRkxNewVRlBghQyNIwCGz992CBpsLfvJ9eJ+6uhDftQ KBQxHWvyYGdosrXwwvXt7IStzsZkCooC+tWeDLYXJBQN5fabTzthUSmEI +aSLFoJJ6rMntfJCsxsHcnx6JMjAWYr7f9vH11weCeIbuCJcqfO9wiNFm zSkP0pGGnLy0cuTqOtIjJrFpAj/MeHNxivlPBU8+M6aAGshmm60zpIFTB w==; X-IronPort-AV: E=Sophos;i="6.03,183,1694728800"; d="scan'208";a="33198950" Received: from vtuxmail01.tq-net.de ([10.115.0.20]) by mx1.tq-group.com with ESMTP; 28 Sep 2023 13:45:30 +0200 Received: from localhost.localdomain (SCHIFFERM-M2.tq-net.de [10.121.49.20]) by vtuxmail01.tq-net.de (Postfix) with ESMTPA id 2318E280084; Thu, 28 Sep 2023 13:45:30 +0200 (CEST) From: Matthias Schiffer To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux@ew.tq-group.com, Matthias Schiffer Subject: [PATCH 2/4] arm64: dts: ti: k3-am64-tqma64xxl-mbax4xxl: add muxing for GPIOs on pin headers Date: Thu, 28 Sep 2023 13:45:11 +0200 Message-Id: <77c30081154774ce31fc4306474a3afa52b07753.1695901360.git.matthias.schiffer@ew.tq-group.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230928_044539_295071_1674FB86 X-CRM114-Status: GOOD ( 12.23 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The pin headers X41 and X42 do not have a fixed function. All of these pins can be assigned to PRG0, but as a default, it makes more sense to configure them as simple GPIOs, as the MBaX4XxL is a starterkit/evaluation mainboard. Signed-off-by: Matthias Schiffer --- .../dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts | 76 ++++++++++++++++++- 1 file changed, 75 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts index 04c15b64f0b77..7c49d30587d25 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts @@ -170,7 +170,8 @@ &main_gpio0 { &main_gpio1 { pinctrl-names = "default"; - pinctrl-0 = <&main_gpio1_hog_pins>; + pinctrl-0 = <&main_gpio1_hog_pins>, + <&main_gpio1_pru_pins>; gpio-line-names = "", "", "", "", /* 0-3 */ "", "", "", "", /* 4-7 */ @@ -545,6 +546,79 @@ AM64X_IOPAD(0x0278, PIN_INPUT, 7) >; }; + main_gpio1_pru_pins: main-gpio1-pru-pins { + pinctrl-single,pins = < + /* (Y1) PRG0_PRU0_GPO0.GPIO1_0 */ + AM64X_IOPAD(0x0160, PIN_INPUT, 7) + /* (R4) PRG0_PRU0_GPO1.GPIO1_1 */ + AM64X_IOPAD(0x0164, PIN_INPUT, 7) + /* (U2) PRG0_PRU0_GPO2.GPIO1_2 */ + AM64X_IOPAD(0x0168, PIN_INPUT, 7) + /* (V2) PRG0_PRU0_GPO3.GPIO1_3 */ + AM64X_IOPAD(0x016c, PIN_INPUT, 7) + /* (AA2) PRG0_PRU0_GPO4.GPIO1_4 */ + AM64X_IOPAD(0x0170, PIN_INPUT, 7) + /* (R3) PRG0_PRU0_GPO5.GPIO1_5 */ + AM64X_IOPAD(0x0174, PIN_INPUT, 7) + /* (T3) PRG0_PRU0_GPO6.GPIO1_6 */ + AM64X_IOPAD(0x0178, PIN_INPUT, 7) + /* (T1) PRG0_PRU0_GPO7.GPIO1_7 */ + AM64X_IOPAD(0x017c, PIN_INPUT, 7) + /* (T2) PRG0_PRU0_GPO8.GPIO1_8 */ + AM64X_IOPAD(0x0180, PIN_INPUT, 7) + /* (Y3) PRG0_PRU0_GPO11.GPIO1_11 */ + AM64X_IOPAD(0x018c, PIN_INPUT, 7) + /* (AA3) PRG0_PRU0_GPO12.GPIO1_12 */ + AM64X_IOPAD(0x0190, PIN_INPUT, 7) + /* (R6) PRG0_PRU0_GPO13.GPIO1_13 */ + AM64X_IOPAD(0x0194, PIN_INPUT, 7) + /* (V4) PRG0_PRU0_GPO14.GPIO1_14 */ + AM64X_IOPAD(0x0198, PIN_INPUT, 7) + /* (T5) PRG0_PRU0_GPO15.GPIO1_15 */ + AM64X_IOPAD(0x019c, PIN_INPUT, 7) + /* (U4) PRG0_PRU0_GPO16.GPIO1_16 */ + AM64X_IOPAD(0x01a0, PIN_INPUT, 7) + /* (U1) PRG0_PRU0_GPO17.GPIO1_17 */ + AM64X_IOPAD(0x01a4, PIN_INPUT, 7) + /* (V1) PRG0_PRU0_GPO18.GPIO1_18 */ + AM64X_IOPAD(0x01a8, PIN_INPUT, 7) + /* (W1) PRG0_PRU0_GPO19.GPIO1_19 */ + AM64X_IOPAD(0x01ac, PIN_INPUT, 7) + /* (Y2) PRG0_PRU1_GPO0.GPIO1_20 */ + AM64X_IOPAD(0x01b0, PIN_INPUT, 7) + /* (W2) PRG0_PRU1_GPO1.GPIO1_21 */ + AM64X_IOPAD(0x01b4, PIN_INPUT, 7) + /* (V3) PRG0_PRU1_GPO2.GPIO1_22 */ + AM64X_IOPAD(0x01b8, PIN_INPUT, 7) + /* (T4) PRG0_PRU1_GPO3.GPIO1_23 */ + AM64X_IOPAD(0x01bc, PIN_INPUT, 7) + /* (W3) PRG0_PRU1_GPO4.GPIO1_24 */ + AM64X_IOPAD(0x01c0, PIN_INPUT, 7) + /* (P4) PRG0_PRU1_GPO5.GPIO1_25 */ + AM64X_IOPAD(0x01c4, PIN_INPUT, 7) + /* (R5) PRG0_PRU1_GPO6.GPIO1_26 */ + AM64X_IOPAD(0x01c8, PIN_INPUT, 7) + /* (R1) PRG0_PRU1_GPO8.GPIO1_28 */ + AM64X_IOPAD(0x01d0, PIN_INPUT, 7) + /* (W4) PRG0_PRU1_GPO11.GPIO1_31 */ + AM64X_IOPAD(0x01dc, PIN_INPUT, 7) + /* (Y4) PRG0_PRU1_GPO12.GPIO1_32 */ + AM64X_IOPAD(0x01e0, PIN_INPUT, 7) + /* (T6) PRG0_PRU1_GPO13.GPIO1_33 */ + AM64X_IOPAD(0x01e4, PIN_INPUT, 7) + /* (U6) PRG0_PRU1_GPO14.GPIO1_34 */ + AM64X_IOPAD(0x01e8, PIN_INPUT, 7) + /* (U5) PRG0_PRU1_GPO15.GPIO1_35 */ + AM64X_IOPAD(0x01ec, PIN_INPUT, 7) + /* (AA4) PRG0_PRU1_GPO16.GPIO1_36 */ + AM64X_IOPAD(0x01f0, PIN_INPUT, 7) + /* (P2) PRG0_MDIO0_MDIO.GPIO1_40 */ + AM64X_IOPAD(0x0200, PIN_INPUT, 7) + /* (P3) PRG0_MDIO0_MDC.GPIO1_41 */ + AM64X_IOPAD(0x0204, PIN_INPUT, 7) + >; + }; + main_mcan0_pins: main-mcan0-pins { pinctrl-single,pins = < /* (B17) MCAN0_RX */