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Fri, 12 Apr 2024 20:44:04 -0700 From: Nicolin Chen To: , CC: , , , , , , , , Subject: [PATCH v5 3/6] iommu/arm-smmu-v3: Make __arm_smmu_cmdq_skip_err reusable Date: Fri, 12 Apr 2024 20:43:51 -0700 Message-ID: <7aaecf0eab666d3f074adc0186dd13e9fbf17061.1712977210.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099D4:EE_|CY8PR12MB7633:EE_ X-MS-Office365-Filtering-Correlation-Id: a0058ad5-8153-415d-edec-08dc5b6bfa43 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: c7FnlR/J5xuCvFFt8PfbreoSMwKySPZbgNFDc+DGZoXP9Ds5V+8jJCz5aFTtJXJ8eauHNUVy2B4oT1OwgTcJnspjyx736Qbkp9/0cASufWw15x75uYMNED1mpRpCqlw94JTCoTS8u98BF83tIBTJBGVdgMuZKF4xveOUP40pKz/1lSA20Xa4SVafPrl6MldfI/EHTYbgK+MVHZVczGJbKLnGXmGzbGcLDNd5vRvXSuA41SNhFWOBtZxmtaIDqZ/HrlvQ9Fp8M+l3lhpL08tgMUdfWmikzLHyCWzMQZ5lneQqg5/DepVFW0V77jvNCxbpbEqgR2F33UFfmDAx9vQ4yz7qMDV7FK/hYj0JiH73r/FtSzmqDtxM3x/e3gJMRwCkeLi8XsFlHyJA9X77p+rDBfKsjtgQKnWuMQUPqTmiH47+JDPFvt4kgkC4CdsALa6e2onnohhCE2HOjf5oN3iMB3ULOrrECK9sG43ABhi/5wvOtO3VFAMJ8aWAbtWAS9OsdMytea9ik39gvUePEz1eB7LGD1VW/DsVC5NBmuBr97kBHPmVjl2JgTpCWBgeFi8m7hQQfLPfGlbqbyhv7W91oLbt/opkpEWHz4PCjt6LBde8tKdAzyHsmCEGTxuZTruic702gGDcQUT0dHpw5JuXs4xTESbA/g1TzYH0KLzkMLwu1j0CrvIScXMRDtuMpsAUiFjXRUzOw0+jOikUXcW+FYQTQI5V46GO3f5AcHFfmBC2JMhPKzrEHVruZ8u6EkpI X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230031)(82310400014)(376005)(1800799015)(36860700004);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Apr 2024 03:44:09.6589 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a0058ad5-8153-415d-edec-08dc5b6bfa43 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D4.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7633 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240412_204423_200581_E53044B8 X-CRM114-Status: GOOD ( 11.89 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Allow __arm_smmu_cmdq_skip_err function to be reused by NVIDIA Tegra241 CMDQV unit since it will use the same data structure for q. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 16 +++++++++------- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 18da1a317823..c5d43f2167be 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -379,8 +379,7 @@ static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu, arm_smmu_cmdq_build_cmd(cmd, &ent); } -static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, - struct arm_smmu_queue *q) +void __arm_smmu_cmdq_skip_err(struct device *dev, struct arm_smmu_queue *q) { static const char * const cerror_str[] = { [CMDQ_ERR_CERROR_NONE_IDX] = "No error", @@ -397,12 +396,12 @@ static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, .opcode = CMDQ_OP_CMD_SYNC, }; - dev_err(smmu->dev, "CMDQ error (cons 0x%08x): %s\n", cons, + dev_err(dev, "CMDQ error (cons 0x%08x): %s\n", cons, idx < ARRAY_SIZE(cerror_str) ? cerror_str[idx] : "Unknown"); switch (idx) { case CMDQ_ERR_CERROR_ABT_IDX: - dev_err(smmu->dev, "retrying command fetch\n"); + dev_err(dev, "retrying command fetch\n"); return; case CMDQ_ERR_CERROR_NONE_IDX: return; @@ -424,9 +423,12 @@ static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, * not to touch any of the shadow cmdq state. */ queue_read(cmd, Q_ENT(q, cons), q->ent_dwords); - dev_err(smmu->dev, "skipping command in error state:\n"); + dev_err(dev, "skipping command in error state:\n"); for (i = 0; i < ARRAY_SIZE(cmd); ++i) - dev_err(smmu->dev, "\t0x%016llx\n", (unsigned long long)cmd[i]); + dev_err(dev, "\t0x%016llx\n", (unsigned long long)cmd[i]); + + if (q->quirks & CMDQ_QUIRK_SYNC_CS_NONE_ONLY) + cmd_sync.sync.cs_none = true; /* Convert the erroneous command into a CMD_SYNC */ arm_smmu_cmdq_build_cmd(cmd, &cmd_sync); @@ -436,7 +438,7 @@ static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, static void arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu) { - __arm_smmu_cmdq_skip_err(smmu, &smmu->cmdq.q); + __arm_smmu_cmdq_skip_err(smmu->dev, &smmu->cmdq.q); } /* diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index ab2824e46ac5..ce0b0afe62b8 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -762,6 +762,7 @@ int arm_smmu_atc_inv_domain(struct arm_smmu_domain *smmu_domain, int ssid, int arm_smmu_cmdq_init(struct arm_smmu_device *smmu, struct arm_smmu_cmdq *cmdq); +void __arm_smmu_cmdq_skip_err(struct device *dev, struct arm_smmu_queue *q); #ifdef CONFIG_ARM_SMMU_V3_SVA bool arm_smmu_sva_supported(struct arm_smmu_device *smmu);