From patchwork Thu Feb 6 04:44:51 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush ANAND X-Patchwork-Id: 3592841 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 172949F288 for ; Thu, 6 Feb 2014 04:49:01 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 15AB82015D for ; Thu, 6 Feb 2014 04:49:00 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E8A5020125 for ; Thu, 6 Feb 2014 04:48:58 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WBGrR-0005M3-Qh; Thu, 06 Feb 2014 04:46:50 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WBGr1-0002ET-Ix; Thu, 06 Feb 2014 04:46:23 +0000 Received: from eu1sys200aog110.obsmtp.com ([207.126.144.129]) by merlin.infradead.org with smtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WBGqW-0002A1-BP for linux-arm-kernel@lists.infradead.org; Thu, 06 Feb 2014 04:45:55 +0000 Received: from beta.dmz-ap.st.com ([138.198.100.35]) (using TLSv1) by eu1sys200aob110.postini.com ([207.126.147.11]) with SMTP ID DSNKUvMTY08BdtWbuf8hPIgVW8r0Uii8he9R@postini.com; Thu, 06 Feb 2014 04:45:51 UTC Received: from zeta.dmz-ap.st.com (ns6.st.com [138.198.234.13]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 7A39BB4; Thu, 6 Feb 2014 04:45:14 +0000 (GMT) Received: from Webmail-ap.st.com (eapex1hubcas4.st.com [10.80.176.69]) by zeta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 61A6514E5; Thu, 6 Feb 2014 04:45:14 +0000 (GMT) Received: from localhost (10.199.210.48) by Webmail-ap.st.com (10.80.176.7) with Microsoft SMTP Server (TLS) id 8.3.297.1; Thu, 6 Feb 2014 12:45:14 +0800 From: Pratyush Anand To: Subject: [PATCH V4 4/8] phy: st-miphy-40lp: Add skeleton driver Date: Thu, 6 Feb 2014 10:14:51 +0530 Message-ID: <8596e7596e0dfa9a487c4c2deb325bbdf785e55e.1391661589.git.pratyush.anand@st.com> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140205_234552_792130_7C6FB835 X-CRM114-Status: GOOD ( 20.63 ) X-Spam-Score: -4.2 (----) Cc: Pratyush Anand , devicetree@vger.kernel.org, spear-devel@list.st.com, linux-kernel@vger.kernel.org, Kishon Vijay Abraham I , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP ST miphy-40lp supports PCIe, SATA and Super Speed USB. This driver adds skeleton support for the same. Currently phy ops are returning -EINVAL. They can be elaborated depending on the SOC being supported in future. Signed-off-by: Pratyush Anand Tested-by: Mohit Kumar Cc: Arnd Bergmann Cc: Kishon Vijay Abraham I Cc: spear-devel@list.st.com Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org --- .../devicetree/bindings/phy/st-miphy40lp.txt | 12 ++ drivers/phy/Kconfig | 6 + drivers/phy/Makefile | 1 + drivers/phy/phy-miphy40lp.c | 174 +++++++++++++++++++++ 4 files changed, 193 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/st-miphy40lp.txt create mode 100644 drivers/phy/phy-miphy40lp.c diff --git a/Documentation/devicetree/bindings/phy/st-miphy40lp.txt b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt new file mode 100644 index 0000000..d0c7096 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt @@ -0,0 +1,12 @@ +Required properties: +- compatible : should be "st,miphy40lp-phy" + Other supported soc specific compatible: + "st,spear1310-miphy" + "st,spear1340-miphy" +- reg : offset and length of the PHY register set. +- misc: phandle for the syscon node to access misc registers +- phy-id: Instance id of the phy. +- #phy-cells : from the generic PHY bindings, must be 1. + - 1st cell: phandle to the phy node. + - 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe + and 2 for Super Speed USB. diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index afa2354..2f58993 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -64,4 +64,10 @@ config BCM_KONA_USB2_PHY help Enable this to support the Broadcom Kona USB 2.0 PHY. +config PHY_ST_MIPHY40LP + tristate "ST MIPHY 40LP driver" + help + Support for ST MIPHY 40LP which can be used for PCIe, SATA and Super Speed USB. + select GENERIC_PHY + endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index b57c253..c061091 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o +obj-$(CONFIG_PHY_ST_MIPHY40LP) += phy-miphy40lp.o diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c new file mode 100644 index 0000000..d478c14 --- /dev/null +++ b/drivers/phy/phy-miphy40lp.c @@ -0,0 +1,174 @@ +/* + * ST MiPHY-40LP PHY driver + * + * Copyright (C) 2014 ST Microelectronics + * Pratyush Anand + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +enum phy_mode { + SATA, + PCIE, + SS_USB, +}; + +struct st_miphy40lp_priv { + /* regmap for any soc specific misc registers */ + struct regmap *misc; + /* phy struct pointer */ + struct phy *phy; + /* device node pointer */ + struct device_node *np; + /* phy mode: 0 for SATA 1 for PCIe and 2 for SS-USB */ + enum phy_mode mode; + /* instance id of this phy */ + u32 id; +}; + +static int miphy40lp_init(struct phy *phy) +{ + return -EINVAL; +} + +static int miphy40lp_exit(struct phy *phy) +{ + return -EINVAL; +} + +static int miphy40lp_power_off(struct phy *phy) +{ + return -EINVAL; +} + +static int miphy40lp_power_on(struct phy *phy) +{ + return -EINVAL; +} + +static const struct of_device_id st_miphy40lp_of_match[] = { + { .compatible = "st,miphy40lp-phy" }, + { }, +}; +MODULE_DEVICE_TABLE(of, st_miphy40lp_of_match); + +static struct phy_ops st_miphy40lp_ops = { + .init = miphy40lp_init, + .exit = miphy40lp_exit, + .power_off = miphy40lp_power_off, + .power_on = miphy40lp_power_on, + .owner = THIS_MODULE, +}; + +#ifdef CONFIG_PM_SLEEP +static int miphy40lp_suspend(struct device *dev) +{ + return -EINVAL; +} + +static int miphy40lp_resume(struct device *dev) +{ + return -EINVAL; +} +#endif + +static SIMPLE_DEV_PM_OPS(miphy40lp_pm_ops, miphy40lp_suspend, + miphy40lp_resume); + +static struct phy *st_miphy40lp_xlate(struct device *dev, + struct of_phandle_args *args) +{ + struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev); + + if (args->args_count < 1) { + dev_err(dev, "DT did not pass correct no of args\n"); + return NULL; + } + + phypriv->mode = args->args[0]; + + return phypriv->phy; +} + +static int __init st_miphy40lp_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct st_miphy40lp_priv *phypriv; + struct phy_provider *phy_provider; + + phypriv = devm_kzalloc(dev, sizeof(*phypriv), GFP_KERNEL); + if (!phypriv) { + dev_err(dev, "can't alloc miphy40lp private date memory\n"); + return -ENOMEM; + } + + phypriv->np = dev->of_node; + + phypriv->misc = + syscon_regmap_lookup_by_phandle(dev->of_node, "misc"); + if (IS_ERR(phypriv->misc)) { + dev_err(dev, "failed to find misc regmap\n"); + return PTR_ERR(phypriv->misc); + } + + if (of_property_read_u32(dev->of_node, "phy-id", &phypriv->id)) { + dev_err(dev, "failed to find phy id\n"); + return -EINVAL; + } + + phy_provider = devm_of_phy_provider_register(dev, st_miphy40lp_xlate); + if (IS_ERR(phy_provider)) { + dev_err(dev, "failed to register phy provider\n"); + return PTR_ERR(phy_provider); + } + + phypriv->phy = devm_phy_create(dev, &st_miphy40lp_ops, NULL); + if (IS_ERR(phypriv->phy)) { + dev_err(dev, "failed to create SATA PCIe PHY\n"); + return PTR_ERR(phypriv->phy); + } + + dev_set_drvdata(dev, phypriv); + phy_set_drvdata(phypriv->phy, phypriv); + + return 0; +} + +static int __exit st_miphy40lp_remove(struct platform_device *pdev) +{ + return 0; +} + +static struct platform_driver st_miphy40lp_driver = { + .remove = __exit_p(st_miphy40lp_remove), + .driver = { + .name = "miphy40lp-phy", + .owner = THIS_MODULE, + .pm = &miphy40lp_pm_ops, + .of_match_table = of_match_ptr(st_miphy40lp_of_match), + }, +}; + +static int __init st_miphy40lp_init(void) +{ + + return platform_driver_probe(&st_miphy40lp_driver, + st_miphy40lp_probe); +} +module_init(st_miphy40lp_init); + +MODULE_DESCRIPTION("ST MIPHY-40LP driver"); +MODULE_AUTHOR("Pratyush Anand "); +MODULE_LICENSE("GPL v2");