| Message ID | 8761epwgni.fsf@free.fr (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
2014-11-09 0:01 GMT+03:00 Robert Jarzmik <robert.jarzmik@free.fr>: > Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> writes: > >> 2014-11-08 20:26 GMT+03:00 Robert Jarzmik <robert.jarzmik@free.fr>: >>> Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> writes: >>> >>>> Hello, >>>> Tested in qemu (pxa25x target). >>>> >>>> 2) sa1100-rtc could not find a clock and thus failed to be probed. >>>> 4) Got an issue with IrDA driver - it gets -ENODEV for UARTCLK clock >>> >>> Hi Dmitry, >>> >>> Would you mind retesting with the patch in [1] applied to see if points 2 and 4 >>> are fixed ? Alternatively you can refetch from the github tree, I included that >>> incremental patch there too. >>> >>> If it works correctly for you, could I have your Tested-by ? If not, tell me and >>> I'll try to figure out what's wrong. >> >> Tested in qemu, everything works fine. I will test on the real hardware >> tomorow. > Aha, the test. > Would you at that time do a "cat /sys/kernel/debug/clk/clk_summary" and send it > to me please ? Tested-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Captured on tosa (pxa255): clock enable_cnt prepare_cnt rate accuracy phase ---------------------------------------------------------------------------------------- clk_dummy 0 0 0 0 0 osc_32_768khz 3 3 32768000 0 0 OSTIMER0 1 1 32768000 0 0 sa1100-rtc 1 1 32768000 0 0 GPIO12_CLK 0 0 32768000 0 0 pxa26x-gpio 0 0 32768000 0 0 pxa25x-gpio 1 1 32768000 0 0 osc_3_6864mhz 3 3 3686400 0 0 PWM1 0 0 3686400 0 0 PWM0 0 0 3686400 0 0 ASSP 0 0 3686400 0 0 NSSP 0 0 3686400 0 0 SSP 0 0 3686400 0 0 GPIO11_CLK 1 1 3686400 0 0 cpll 0 0 398131200 0 0 core 0 0 398131200 0 0 run 0 0 199065600 0 0 MEMC 0 0 199065600 0 0 LCD 0 0 199065600 0 0 memory 0 0 99532800 0 0 ppll_147_46mhz 2 4 147456000 0 0 AC97 1 1 12288000 0 0 I2S 0 0 147456000 0 0 HWUART 0 0 14745600 0 0 STUART 0 1 14745600 0 0 pxa2xx-ir 0 0 14745600 0 0 BTUART 0 1 14745600 0 0 FFUART 1 2 14745600 0 0 ppll_95_85mhz 1 1 95846400 0 0 USB 0 0 47923200 0 0 FICP 0 0 47923200 0 0 I2C 1 1 31948800 0 0 MMC 0 0 19169280 0 0 >> BTW: It looks like pxa27x also shows the same behaviour wrt. sa1100-rtc and >> pxa2xx-ir (after reverting a revert). > Ah yes, you're very right about that. > > Same as before, github updated and patch included in this mail. Could you please also include a revert of 23c4a3a5212701ad34bd30591fa33d7bacef9c5f into your branch? Otherwise pxa27x is broken in your tree. > > Cheers. > > -- > Robert >
Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> writes: > 2014-11-09 0:01 GMT+03:00 Robert Jarzmik <robert.jarzmik@free.fr>: > Tested-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> OK, that's really great, thanks for your testing effort. I'll digest the clk_summary output next week to cross-check everything is in order. > Could you please also include a revert of > 23c4a3a5212701ad34bd30591fa33d7bacef9c5f > into your branch? Otherwise pxa27x is broken in your tree. Done. I will release v2 of this serie very soon now as the fixes for at least 2 pxa25x platforms are identified and done. Cheers.
Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> writes: > 2014-11-09 0:01 GMT+03:00 Robert Jarzmik <robert.jarzmik@free.fr>: > clock enable_cnt prepare_cnt rate > accuracy phase > ---------------------------------------------------------------------------------------- > clk_dummy 0 0 0 > 0 0 > osc_32_768khz 3 3 32768000 Here the clock rate should be 1000 times slower, for v3. > ppll_147_46mhz 2 4 147456000 > 0 0 > AC97 1 1 12288000 This is not the same value as before, but given that the manual states this value and that AC97 clock's rate is not used by its driver (probably because the clock is driven by the codec if I remember correctly), that will stay this way. > 0 0 > I2S 0 0 147456000 Here to clock rate is 10 times too quick, for v3. Cheers.
From c36803b312621c1a69d2d6aed000ae7ee11da588 Mon Sep 17 00:00:00 2001 From: Robert Jarzmik <robert.jarzmik@free.fr> Date: Sat, 8 Nov 2014 21:46:51 +0100 Subject: [PATCH] clk: pxa: add missing clocks for Irda and sa1100-rtc Add 2 clocks which were erronously forgotten by the clock framework port, namely : - sa1100-rtc - irda for pxa2xx-ir:UARTCLK Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> --- drivers/clk/pxa/clk-pxa27x.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/clk/pxa/clk-pxa27x.c b/drivers/clk/pxa/clk-pxa27x.c index 2b8343a..611879b 100644 --- a/drivers/clk/pxa/clk-pxa27x.c +++ b/drivers/clk/pxa/clk-pxa27x.c @@ -353,6 +353,33 @@ static u8 clk_pxa27x_memory_get_parent(struct clk_hw *hw) PARENTS(clk_pxa27x_memory) = { "osc_13mhz", "system_bus", "run" }; MUX_RO_RATE_RO_OPS(clk_pxa27x_memory, "memory"); +#define DUMMY_CLK(_con_id, _dev_id, _parent) \ + { .con_id = _con_id, .dev_id = _dev_id, .parent = _parent } +struct dummy_clk { + const char *con_id; + const char *dev_id; + const char *parent; +}; +static struct dummy_clk dummy_clks[] __initdata = { + DUMMY_CLK(NULL, "sa1100-rtc", "osc_32_768khz"), + DUMMY_CLK("UARTCLK", "pxa2xx-ir", "STUART"), +}; + +static void __init pxa27x_dummy_clocks_init(void) +{ + struct clk *clk; + struct dummy_clk *d; + const char *name; + int i; + + for (i = 0; i < ARRAY_SIZE(dummy_clks); i++) { + d = &dummy_clks[i]; + name = d->dev_id ? d->dev_id : d->con_id; + clk = clk_register_fixed_factor(NULL, name, d->parent, 0, 1, 1); + clk_register_clkdev(clk, d->con_id, d->dev_id); + } +} + static void __init pxa27x_base_clocks_init(void) { pxa27x_register_plls(); @@ -365,6 +392,7 @@ static void __init pxa27x_base_clocks_init(void) int __init pxa27x_clocks_init(void) { pxa27x_base_clocks_init(); + pxa27x_dummy_clocks_init(); return clk_pxa_cken_init(pxa27x_clocks, ARRAY_SIZE(pxa27x_clocks)); } -- 2.1.0