diff mbox series

[v3,3/3] arm64: dts: ipq6018: add pwm node

Message ID 87b49aeaa55c3ca65e31ea70286e2e563816c660.1624348502.git.baruch@tkos.co.il (mailing list archive)
State New, archived
Headers show
Series [v3,1/3] pwm: driver for qualcomm ipq6018 pwm block | expand

Commit Message

Baruch Siach June 22, 2021, 7:55 a.m. UTC
Describe the PWM block on IPQ6018.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
---
Rob has not responded to Bjorn's questions[1] regarding registers area
description and the TCSR block. Leaving it the same as in v2 for now.

[1] https://lore.kernel.org/linux-arm-msm/YLgO0Aj1d4w9EcPv@yoga/

v3: s/qcom,pwm-ipq6018/qcom,ipq6018-pwm/ (Rob Herring)
---
 arch/arm64/boot/dts/qcom/ipq6018.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index 6ee7b99c21ec..bbc1ed960bb4 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -355,6 +355,15 @@  i2c_1: i2c@78b7000 { /* BLSP1 QUP2 */
 			status = "disabled";
 		};
 
+		pwm: pwm@1941010 {
+			#pwm-cells = <2>;
+			compatible = "qcom,ipq6018-pwm";
+			reg = <0x0 0x1941010 0x0 0x20>;
+			clocks = <&gcc GCC_ADSS_PWM_CLK>;
+			clock-names = "core";
+			status = "disabled";
+		};
+
 		qpic_bam: dma-controller@7984000 {
 			compatible = "qcom,bam-v1.7.0";
 			reg = <0x0 0x07984000 0x0 0x1a000>;