From patchwork Fri Nov 21 21:32:48 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Jarzmik X-Patchwork-Id: 5358131 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 954309F1E1 for ; Fri, 21 Nov 2014 21:35:27 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D2781201FA for ; Fri, 21 Nov 2014 21:35:26 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D2499200F0 for ; Fri, 21 Nov 2014 21:35:25 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XrvpR-0001wo-Rl; Fri, 21 Nov 2014 21:33:21 +0000 Received: from smtp06.smtpout.orange.fr ([80.12.242.128] helo=smtp.smtpout.orange.fr) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XrvpO-0001v4-C9 for linux-arm-kernel@lists.infradead.org; Fri, 21 Nov 2014 21:33:19 +0000 Received: from beldin ([109.222.88.20]) by mwinf5d12 with ME id JMYo1p00D0SLQZp03MYobN; Fri, 21 Nov 2014 22:32:56 +0100 X-ME-Helo: beldin X-ME-Date: Fri, 21 Nov 2014 22:32:56 +0100 X-ME-IP: 109.222.88.20 From: Robert Jarzmik To: Marc Zyngier , Dmitry Eremin-Solenikov Subject: Re: IRQ #0 broken on ARM References: <87zjbk966i.fsf@approximate.cambridge.arm.com> <20141121110135.GS4042@n2100.arm.linux.org.uk> <546F1F45.7080103@arm.com> X-URL: http://belgarath.falguerolles.org/ Date: Fri, 21 Nov 2014 22:32:48 +0100 In-Reply-To: <546F1F45.7080103@arm.com> (Marc Zyngier's message of "Fri, 21 Nov 2014 11:17:25 +0000") Message-ID: <87egsw5jen.fsf@free.fr> User-Agent: Gnus/5.130008 (Ma Gnus v0.8) Emacs/24.3.92 (gnu/linux) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141121_133318_581330_0CA8BE74 X-CRM114-Status: GOOD ( 13.42 ) X-Spam-Score: 0.0 (/) Cc: Andrea Adami , Thomas Gleixner , Russell King - ARM Linux , linux-arm-kernel X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00,FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Marc Zyngier writes: >> Linus has decreed it to not be a valid IRQ number, and that's basically >> the end of the discussion. Generic code, and drivers, will increasingly >> decide that IRQ0 is not valid, and objecting to it has, and will continue >> to elicit a response of "fix ARM". > > I'm fine with that. For pxa, why not do something like that [1] ? Cheers. --- Robert [1] ---8>--- From 551eaf75934bd84939a40781470ed3c04d17507a Mon Sep 17 00:00:00 2001 From: Robert Jarzmik Date: Fri, 21 Nov 2014 22:11:42 +0100 Subject: [PATCH] ARM: pxa: arbitrarily set first interrupt number As IRQ0, the legacy timer interrupt should not be used as an interrupt number, shift the interrupts by a fixed number. As we had in a special case a shift of 16 when ISA bus was used on a PXA, use that value as the first interrupt number, regardless of ISA or not. Signed-off-by: Robert Jarzmik --- arch/arm/mach-pxa/include/mach/irqs.h | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/arm/mach-pxa/include/mach/irqs.h b/arch/arm/mach-pxa/include/mach/irqs.h index 48c2fd8..9d8983f 100644 --- a/arch/arm/mach-pxa/include/mach/irqs.h +++ b/arch/arm/mach-pxa/include/mach/irqs.h @@ -14,12 +14,9 @@ #ifdef CONFIG_PXA_HAVE_ISA_IRQS #define PXA_ISA_IRQ(x) (x) -#define PXA_ISA_IRQ_NUM (16) -#else -#define PXA_ISA_IRQ_NUM (0) #endif -#define PXA_IRQ(x) (PXA_ISA_IRQ_NUM + (x)) +#define PXA_IRQ(x) (16 + (x)) #define IRQ_SSP3 PXA_IRQ(0) /* SSP3 service request */ #define IRQ_MSL PXA_IRQ(1) /* MSL Interface interrupt */