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Thu, 29 Aug 2024 15:34:50 -0700 From: Nicolin Chen To: CC: , , , , , , , , , Subject: [PATCH v14 07/10] iommu/arm-smmu-v3: Add struct arm_smmu_impl_ops Date: Thu, 29 Aug 2024 15:34:36 -0700 Message-ID: <8fe9f3805568aabf771fc6706c116459016bf62d.1724970714.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397AE:EE_|CH3PR12MB8257:EE_ X-MS-Office365-Filtering-Correlation-Id: d0db0b7e-d2e9-4152-684f-08dcc87ad559 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: S5vXADP37gJxCHE3wPUSBPjvMzQYFy+UyFzXnOvaRknYY3rLudm8/MDGRXfqrI/eFFdmEvCt20W+Ue+/7Utf4jvlVZLLccOoQFMTsfgeugDwXOo4lyjkyC1ZNa2GcOZ8LTx+NyAeJ4GRNXd4d7bmypCSop4DRfcWy7kceLEe2SVCiT4a5BwEIsf3qxaTOsNiQwQSUJ5zQEDCyCCtL+rh+OCIyIU1Jjd+LLqm07pdmo072ulzTK0avIODhTfdM30sy89Z4mPs6kgXIINiVMHiL2YkMo58Xa56nhdZZkAiyzhhCl+F8xi1Olgu+8moRjIHr42nfh0zonpRLXv6Ngf6pIz0OjvpMjyHRKyqzO6HEbnMuMRxUZxbYt76Ctu65tdKEUdGNaHKCOEWDQ8UO5o0b5HyM+yTOJHVQ8NkipEaufcQBgy172+73GeMUSb1kKjpd24vF/lqZTn5Q6rpxnU0ZxUr/peKE0jcDXpZaeKNnptp5dz+lNZ01Z0Rh/c9Ns9ow/foWqsmvur7QiY8fwYxlnIuYDpP7Ti2kRxYyIil5UD4g5u4TmnEpW6LzpcAODws+3/ZG+Bd400vl2sRvWOeYbEwNZpMIEbNhHObkds5S4BN3mum2wpcaQTyAvPCH45O7ZIBCUGR4xNnS+Go+/FWz1oUheZyhTG5W5kAnM3PQStZdxHro+wSkQAmayyj5MC59LDEWjZ0xJVxKeH7NVP51kTjJ6pQfYnm8axW42bJOrNfl7tkf7iPV2P//fQthCmyyl82qZ54OgptPN/vWkP2f817iRx+zhhfdO3h0gBzg8i/wYCc+8TqNbJAUHfIGFmsL7mCqanUeEk2CFmdF9PTQdSawDBMFdXvclKW27izgaluxa4HzBEFpuELD4UM16LRtPk+oUFvAUAktWNm0mA59cy+13Ze6mhRPO+lmvNOJrPc/w28R0P2apm9NBaY+Z6j6+EmxOoGEUr4qb19+2SlXBrowC7blcJyLz36PQZlEIJ/808uNeIcicI7cgKEBPmal4ZpbTbmmgW2KzLMIMUv0e8BQdiNSFVFX5w8XbEyUNT9Wa1JBwoHy8ZzntiuIyyg6SXd9XXOwk/v9DVaYBmxpEtwP4xQ/hnicmH5mPr6U8UpTk4gZcGM0SuQd8IhYWOUb+PUV+BSwdU+/aR4AzzVmj4c8f7Y348n8PnxKI9KsdIYKtjg/uOKhrM4b4pdKirHv+zEuZNzT/7z3allmdUIw1VvOvEwOAMuL3Itr3E433GB+PgpLMLR0IVc8zEFLPzlpQq4xoWloMC5diJwHm39HZ3M3nXbme2Hwq+VGCl1l+z0NlF6CILpZ681torUfGimD2Pg6q1byrE+VoLbF0b6jXeUI/aiD+8yyYObg+0V/dwL6ZDzpm9B1DnM0B8DVG+ZKVB/CBKLkirHGbmPbjqePqWyiA9+y2rCfwe+ez866I8N/mgo5vv9tR/Ky/dvsW8s X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Aug 2024 22:35:06.9176 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d0db0b7e-d2e9-4152-684f-08dcc87ad559 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397AE.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8257 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240829_153513_387869_5DF4927F X-CRM114-Status: GOOD ( 19.28 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Jason Gunthorpe Mimicing the arm-smmu (v2) driver, introduce a struct arm_smmu_impl_ops to accommodate impl routines. Suggested-by: Will Deacon Signed-off-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 51 ++++++++++++++++++++- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 10 ++++ 2 files changed, 60 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 8b1437240ce5..ca7b037f4eae 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -348,7 +348,12 @@ static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent) static struct arm_smmu_cmdq *arm_smmu_get_cmdq(struct arm_smmu_device *smmu) { - return &smmu->cmdq; + struct arm_smmu_cmdq *cmdq = NULL; + + if (smmu->impl_ops && smmu->impl_ops->get_secondary_cmdq) + cmdq = smmu->impl_ops->get_secondary_cmdq(smmu); + + return cmdq ?: &smmu->cmdq; } static bool arm_smmu_cmdq_needs_busy_polling(struct arm_smmu_device *smmu, @@ -4052,6 +4057,14 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu) return ret; } + if (smmu->impl_ops && smmu->impl_ops->device_reset) { + ret = smmu->impl_ops->device_reset(smmu); + if (ret) { + dev_err(smmu->dev, "failed to reset impl\n"); + return ret; + } + } + return 0; } @@ -4469,6 +4482,38 @@ static void arm_smmu_rmr_install_bypass_ste(struct arm_smmu_device *smmu) iort_put_rmr_sids(dev_fwnode(smmu->dev), &rmr_list); } +static void arm_smmu_impl_remove(void *data) +{ + struct arm_smmu_device *smmu = data; + + if (smmu->impl_ops && smmu->impl_ops->device_remove) + smmu->impl_ops->device_remove(smmu); +} + +/* + * Probe all the compiled in implementations. Each one checks to see if it + * matches this HW and if so returns a devm_krealloc'd arm_smmu_device which + * replaces the callers. Otherwise the original is returned or ERR_PTR. + */ +static struct arm_smmu_device *arm_smmu_impl_probe(struct arm_smmu_device *smmu) +{ + struct arm_smmu_device *new_smmu = ERR_PTR(-ENODEV); + int ret; + + /* Add impl probe */ + + if (new_smmu == ERR_PTR(-ENODEV)) + return smmu; + if (IS_ERR(new_smmu)) + return new_smmu; + + ret = devm_add_action_or_reset(new_smmu->dev, arm_smmu_impl_remove, + new_smmu); + if (ret) + return ERR_PTR(ret); + return new_smmu; +} + static int arm_smmu_device_probe(struct platform_device *pdev) { int irq, ret; @@ -4490,6 +4535,10 @@ static int arm_smmu_device_probe(struct platform_device *pdev) if (ret) return ret; + smmu = arm_smmu_impl_probe(smmu); + if (IS_ERR(smmu)) + return PTR_ERR(smmu); + /* Base address */ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 21f034f0ff4c..8d7a95b0dbd9 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -14,6 +14,8 @@ #include #include +struct arm_smmu_device; + /* MMIO registers */ #define ARM_SMMU_IDR0 0x0 #define IDR0_ST_LVL GENMASK(28, 27) @@ -630,9 +632,17 @@ struct arm_smmu_strtab_cfg { u32 strtab_base_cfg; }; +struct arm_smmu_impl_ops { + int (*device_reset)(struct arm_smmu_device *smmu); + void (*device_remove)(struct arm_smmu_device *smmu); + struct arm_smmu_cmdq *(*get_secondary_cmdq)(struct arm_smmu_device *smmu); +}; + /* An SMMUv3 instance */ struct arm_smmu_device { struct device *dev; + const struct arm_smmu_impl_ops *impl_ops; + void __iomem *base; void __iomem *page1;