From patchwork Tue May 24 23:56:28 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Brown X-Patchwork-Id: 814532 Received: from bombadil.infradead.org (bombadil.infradead.org [18.85.46.34]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p4ONwPxx022026 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Tue, 24 May 2011 23:58:46 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by bombadil.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QP1Sm-00068B-PR; Tue, 24 May 2011 23:56:37 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QP1Sk-0005DA-FT; Tue, 24 May 2011 23:56:34 +0000 Received: from wolverine01.qualcomm.com ([199.106.114.254]) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QP1Sg-0005Cr-MS for linux-arm-kernel@lists.infradead.org; Tue, 24 May 2011 23:56:31 +0000 X-IronPort-AV: E=McAfee;i="5400,1158,6356"; a="93421554" Received: from pdmz-css-vrrp.qualcomm.com (HELO mostssh01.qualcomm.com) ([199.106.114.130]) by wolverine01.qualcomm.com with ESMTP/TLS/AES256-SHA; 24 May 2011 16:56:28 -0700 Received: from localhost.qualcomm.com ([127.0.0.1] helo=huya.qualcomm.com) by mostssh01.qualcomm.com with esmtp (Exim 4.71) (envelope-from ) id 1QP1S5-0004Kl-KM; Tue, 24 May 2011 16:55:53 -0700 From: David Brown To: Catalin Marinas Subject: Re: [PATCH v6 00/18] ARM: Add support for the Large Physical Address Extensions References: <1306273164-18217-1-git-send-email-catalin.marinas@arm.com> Date: Tue, 24 May 2011 16:56:28 -0700 In-Reply-To: <1306273164-18217-1-git-send-email-catalin.marinas@arm.com> (Catalin Marinas's message of "Tue, 24 May 2011 22:39:06 +0100") Message-ID: <8yapqn7fyab.fsf@huya.qualcomm.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.3 (gnu/linux) MIME-Version: 1.0 X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110524_195631_038483_0E72A46E X-CRM114-Status: GOOD ( 23.95 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [199.106.114.254 listed in list.dnswl.org] Cc: Russell King - ARM Linux , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Tue, 24 May 2011 23:58:46 +0000 (UTC) On Tue, May 24 2011, Catalin Marinas wrote: > This set of patches adds support for the Large Physical Extensions on > the ARM architecture (available with the Cortex-A15 processor). LPAE > comes with a 3-level page table format (compared to 2-level for the > classic one), allowing up to 40-bit physical address space. Do you expect non LPAE targets to be able to boot with these changes applied (and LPAE enabled)? I am able to build this tree for the MSM8660 (with a minor patch below), but it fails to boot with LPAE enabled. It seems to work fine with LPAE not enabled. I did have to fix the msm timer code to get the branch you mentioned to compile. The return type of the function changed back to 'void' without changing the returns: --- arch/arm/mach-msm/timer.c | 5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c index 50cc0bc..6e659e4 100644 --- a/arch/arm/mach-msm/timer.c +++ b/arch/arm/mach-msm/timer.c @@ -268,7 +268,7 @@ static void __cpuinit msm_local_timer_setup(struct clock_event_device *evt) /* Use existing clock_event for cpu 0 */ if (!smp_processor_id()) - return 0; + return; writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL); @@ -296,7 +296,8 @@ static void __cpuinit msm_local_timer_setup(struct clock_event_device *evt) if (res) { pr_err("local_timer_setup: request_irq failed for %s\n", clock->clockevent.name); - return res; + /* TODO: How to handle this error. */ + return; } clockevents_register_device(evt);