@@ -62,7 +62,6 @@ static const char *at91rm9200_dt_board_compat[] __initconst = {
DT_MACHINE_START(at91rm9200_dt, "Atmel AT91RM9200 (Device Tree)")
.init_time = at91rm9200_dt_timer_init,
.map_io = at91_map_io,
- .init_early = at91_dt_initialize,
.init_machine = rm9200_dt_device_init,
.dt_compat = at91rm9200_dt_board_compat,
MACHINE_END
@@ -41,7 +41,6 @@ static const char *at91_dt_board_compat[] __initconst = {
DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM (Device Tree)")
/* Maintainer: Atmel */
.map_io = at91_map_io,
- .init_early = at91_dt_initialize,
.init_machine = sam9_dt_device_init,
.dt_compat = at91_dt_board_compat,
MACHINE_END
@@ -62,7 +61,6 @@ static const char *at91_9g45_board_compat[] __initconst = {
DT_MACHINE_START(at91sam9g45_dt, "Atmel AT91SAM9G45")
/* Maintainer: Atmel */
.map_io = at91_map_io,
- .init_early = at91_dt_initialize,
.init_machine = sam9g45_dt_device_init,
.dt_compat = at91_9g45_board_compat,
MACHINE_END
@@ -84,7 +82,6 @@ static const char *at91_9x5_board_compat[] __initconst = {
DT_MACHINE_START(at91sam9x5_dt, "Atmel AT91SAM9")
/* Maintainer: Atmel */
.map_io = at91_map_io,
- .init_early = at91_dt_initialize,
.init_machine = sam9x5_dt_device_init,
.dt_compat = at91_9x5_board_compat,
MACHINE_END
@@ -18,9 +18,6 @@
extern void __init at91_map_io(void);
extern void __init at91_alt_map_io(void);
- /* Processors */
-extern void __init at91_dt_initialize(void);
-
/* Timer */
extern void at91rm9200_timer_init(void);
@@ -20,6 +20,7 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
+#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/clk/at91_pmc.h>
@@ -41,6 +42,7 @@ static struct {
} at91_pm_data;
static void (*at91_pm_standby)(void);
+void __iomem *at91_ramc_base[2];
static int at91_pm_valid_state(suspend_state_t state)
{
@@ -224,6 +226,43 @@ void at91_pm_set_standby(void (*at91_standby)(void))
}
}
+static struct of_device_id ramc_ids[] = {
+ { .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
+ { .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
+ { .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby },
+ { .compatible = "atmel,sama5d3-ddramc", .data = at91_ddr_standby },
+ { /*sentinel*/ }
+};
+
+static void at91_dt_ramc(void)
+{
+ struct device_node *np;
+ const struct of_device_id *of_id;
+ int idx = 0;
+ const void *standby = NULL;
+
+ for_each_matching_node_and_match(np, ramc_ids, &of_id) {
+ at91_ramc_base[idx] = of_iomap(np, 0);
+ if (!at91_ramc_base[idx])
+ panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
+
+ if (!standby)
+ standby = of_id->data;
+
+ idx++;
+ }
+
+ if (!idx)
+ panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
+
+ if (!standby) {
+ pr_warn("ramc no standby function available\n");
+ return;
+ }
+
+ at91_pm_set_standby(standby);
+}
+
#ifdef CONFIG_AT91_SLOW_CLOCK
static void __init at91_pm_sram_init(void)
{
@@ -282,6 +321,8 @@ static void __init at91_pm_init(void)
void __init at91_rm9200_pm_init(void)
{
+ at91_dt_ramc();
+
/*
* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
*/
@@ -295,6 +336,7 @@ void __init at91_rm9200_pm_init(void)
void __init at91_sam9260_pm_init(void)
{
+ at91_dt_ramc();
at91_pm_data.memctrl = AT91_MEMCTRL_SDRAMC;
at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
return at91_pm_init();
@@ -302,6 +344,7 @@ void __init at91_sam9260_pm_init(void)
void __init at91_sam9g45_pm_init(void)
{
+ at91_dt_ramc();
at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP;
at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
return at91_pm_init();
@@ -309,6 +352,7 @@ void __init at91_sam9g45_pm_init(void)
void __init at91_sam9x5_pm_init(void)
{
+ at91_dt_ramc();
at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
return at91_pm_init();
@@ -42,7 +42,6 @@ static const char *sama5_dt_board_compat[] __initconst = {
DT_MACHINE_START(sama5_dt, "Atmel SAMA5 (Device Tree)")
/* Maintainer: Atmel */
.map_io = at91_map_io,
- .init_early = at91_dt_initialize,
.init_machine = sama5_dt_device_init,
.dt_compat = sama5_dt_board_compat,
MACHINE_END
@@ -88,7 +87,6 @@ static const char *sama5_alt_dt_board_compat[] __initconst = {
DT_MACHINE_START(sama5_alt_dt, "Atmel SAMA5 (Device Tree)")
/* Maintainer: Atmel */
.map_io = sama5_alt_map_io,
- .init_early = at91_dt_initialize,
.init_machine = sama5_dt_device_init,
.dt_compat = sama5_alt_dt_board_compat,
.l2c_aux_mask = ~0UL,
@@ -28,9 +28,6 @@
struct at91_socinfo at91_soc_initdata;
EXPORT_SYMBOL(at91_soc_initdata);
-void __iomem *at91_ramc_base[2];
-EXPORT_SYMBOL_GPL(at91_ramc_base);
-
static struct map_desc at91_io_desc __initdata __maybe_unused = {
.virtual = (unsigned long)AT91_VA_BASE_SYS,
.pfn = __phys_to_pfn(AT91_BASE_SYS),
@@ -331,45 +328,3 @@ void __init at91_ioremap_matrix(u32 base_addr)
if (!at91_matrix_base)
panic(pr_fmt("Impossible to ioremap at91_matrix_base\n"));
}
-
-static struct of_device_id ramc_ids[] = {
- { .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
- { .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
- { .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby },
- { .compatible = "atmel,sama5d3-ddramc", .data = at91_ddr_standby },
- { /*sentinel*/ }
-};
-
-static void at91_dt_ramc(void)
-{
- struct device_node *np;
- const struct of_device_id *of_id;
- int idx = 0;
- const void *standby = NULL;
-
- for_each_matching_node_and_match(np, ramc_ids, &of_id) {
- at91_ramc_base[idx] = of_iomap(np, 0);
- if (!at91_ramc_base[idx])
- panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
-
- if (!standby)
- standby = of_id->data;
-
- idx++;
- }
-
- if (!idx)
- panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
-
- if (!standby) {
- pr_warn("ramc no standby function available\n");
- return;
- }
-
- at91_pm_set_standby(standby);
-}
-
-void __init at91_dt_initialize(void)
-{
- at91_dt_ramc();
-}