diff mbox series

[6/6] net: stmmac: dwmac-s32cc: Read PTP clock rate when ready

Message ID AM9PR04MB850624C6D994A879E395D3EAE2BD2@AM9PR04MB8506.eurprd04.prod.outlook.com (mailing list archive)
State New, archived
Headers show
Series Add support for Synopsis DWMAC IP on NXP Automotive SoCs | expand

Commit Message

Jan Petrous Aug. 4, 2024, 8:50 p.m. UTC 
The PTP clock is read by stmmac_platform during DT parse.
On S32G/R the clock is not ready and returns 0. Postpone
reading of the clock on PTP init.

Co-developed-by: Andrei Botila <andrei.botila@nxp.org>
Signed-off-by: Andrei Botila <andrei.botila@nxp.org>
Signed-off-by: Jan Petrous (OSS) <jan.petrous@oss.nxp.com>
---
 drivers/net/ethernet/stmicro/stmmac/dwmac-s32cc.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)
diff mbox series

Patch

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32cc.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32cc.c
index 2ef961efa01c..ad05f72fefbf 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32cc.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32cc.c
@@ -149,6 +149,18 @@  static void s32cc_fix_mac_speed(void *priv, unsigned int speed, unsigned int mod
 		dev_err(gmac->dev, "Can't set tx clock\n");
 }
 
+static void s32cc_gmac_ptp_clk_freq_config(struct stmmac_priv *priv)
+{
+	struct plat_stmmacenet_data *plat = priv->plat;
+
+	if (!plat->clk_ptp_ref)
+		return;
+
+	plat->clk_ptp_rate = clk_get_rate(plat->clk_ptp_ref);
+
+	netdev_dbg(priv->dev, "PTP rate %lu\n", plat->clk_ptp_rate);
+}
+
 static int s32cc_dwmac_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
@@ -204,6 +216,7 @@  static int s32cc_dwmac_probe(struct platform_device *pdev)
 	plat->init = s32cc_gmac_init;
 	plat->exit = s32cc_gmac_exit;
 	plat->fix_mac_speed = s32cc_fix_mac_speed;
+	plat->ptp_clk_freq_config = s32cc_gmac_ptp_clk_freq_config;
 
 	plat->bsp_priv = gmac;