From patchwork Tue Oct 29 05:09:52 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Kamensky X-Patchwork-Id: 3106191 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id E01CF9F431 for ; Tue, 29 Oct 2013 05:10:48 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CF29D2034A for ; Tue, 29 Oct 2013 05:10:47 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B4B6020328 for ; Tue, 29 Oct 2013 05:10:46 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vb1Zj-0004bQ-3W; Tue, 29 Oct 2013 05:10:43 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vb1Zg-0003mg-O9; Tue, 29 Oct 2013 05:10:40 +0000 Received: from mail-qa0-f53.google.com ([209.85.216.53]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vb1ZU-0003m0-0P for linux-arm-kernel@lists.infradead.org; Tue, 29 Oct 2013 05:10:28 +0000 Received: by mail-qa0-f53.google.com with SMTP id k15so2668524qaq.19 for ; Mon, 28 Oct 2013 22:09:54 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc:content-type; bh=fog25GBPLJOgwz1HnwxUOQRWTrPH79EXN3AO9uAYhG8=; b=GBrutC6la3rEv4SFFiH9obQVv0gXRA8xoh50GAbdmeo8JUkPQZznKFx6oBUN5dhy2T U5vDd/iGnITaittFakXfQFQ+pFmiu4u37/vQGr392ftELMkVM57A9adaHgrpw1OkJtqq DLTcqD/h2cvQ5Edo7ouCboEhumt0UsmvLaLuKEVvcpGdIzSK11ziefIZPlPZ4HLyby7n IT9n9HjkFfFMgSpxVfrWC9zUEb5WY5KkjV4npVKEEbOKNxqnOIwJqx97U/bFo8siI9iD BbyIXpvD1oDtTMhWbNWWla+RVvtpzFsv28Zm5Cd+2IT/e8Ic7EbY7lzXReek7u0lO5z5 Oeiw== X-Gm-Message-State: ALoCoQnlazP+i+c41BWp7rs2TUaW9UWEeCefBGHSho/+tdQaigTNrum5VBqup/iN8AQgpZKpTcbH MIME-Version: 1.0 X-Received: by 10.229.109.193 with SMTP id k1mr33840119qcp.9.1383023392352; Mon, 28 Oct 2013 22:09:52 -0700 (PDT) Received: by 10.229.171.199 with HTTP; Mon, 28 Oct 2013 22:09:52 -0700 (PDT) In-Reply-To: <526E2A7E.50108@ti.com> References: <20131018205405.GA28835@codethink.co.uk> <20131019170954.GC25076@mudshark.cambridge.arm.com> <5262E2C7.7000106@codethink.co.uk> <20131028004736.GG16735@n2100.arm.linux.org.uk> <20131028084455.GA20218@mudshark.cambridge.arm.com> <20131028085328.GI16735@n2100.arm.linux.org.uk> <526E2A7E.50108@ti.com> Date: Mon, 28 Oct 2013 22:09:52 -0700 Message-ID: Subject: Re: [PULL REQ] Big Endian initial patch series From: Victor Kamensky To: Sricharan R X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131029_011028_107315_DFB1D83D X-CRM114-Status: GOOD ( 21.13 ) X-Spam-Score: -2.6 (--) Cc: "thomas.petazzoni@free-electrons.com" , Russell King - ARM Linux , Will Deacon , Ben Dooks , Dave P Martin , "linux-arm-kernel@lists.infradead.org" X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Hi Sricharan, Another problem with f52bb72 commit is missing .align at the end of __fixup_a_pv_table function. In case of thumb2 kernel address at label 3 could be 2 bytes aligned and cause unaligned access exception. It may work now because it is accidentally 4 bytes aligned but it could change as code evolves. This happened to me while I tried to work out how to deal with this code in BE case (I am still working on that). Thanks, Victor On 28 October 2013 02:12, Sricharan R wrote: > Hi, > On Monday 28 October 2013 02:23 PM, Russell King - ARM Linux wrote: >> On Mon, Oct 28, 2013 at 08:44:55AM +0000, Will Deacon wrote: >>> Hi Russell, >>> >>> On Mon, Oct 28, 2013 at 12:47:36AM +0000, Russell King - ARM Linux wrote: >>>> On Sat, Oct 19, 2013 at 08:51:35PM +0100, Ben Dooks wrote: >>>>> On 19/10/13 18:09, Will Deacon wrote: >>>>>> Do you think you could send another pull request please? >>>>> Ok, sorted. >>>> Pulled, but there was a conflict. Please check this resolution (it's >>>> copy'n'pasted). I'll probably be in linux-next tomorrow in any case, >>>> but any mistake here can be fixed. >>> This doesn't look quite right to me, but unfortunately I'm going be spending >>> most (all?) of today trying to catch a flight out of the UK. Hopefully Dave >>> or Ben can investigate further, but comments below. >>> >>>> diff --cc arch/arm/kernel/head.S >>>> index 54547947a4e9,a047acfa6b6d..000000000000 >>>> --- a/arch/arm/kernel/head.S >>>> +++ b/arch/arm/kernel/head.S >>>> @@@ -602,28 -586,26 +606,39 @@@ __fixup_a_pv_table >>>> b 2f >>>> 1: add r7, r3 >>>> ldrh ip, [r7, #2] >>>> + ARM_BE8(rev16 ip, ip) >>>> - and ip, 0x8f00 >>>> - orr ip, r6 @ mask in offset bits 31-24 >>>> + tst ip, #0x4000 >>>> + and ip, #0x8f00 >>>> + orrne ip, r6 @ mask in offset bits 31-24 >>>> + orreq ip, r0 @ mask in offset bits 7-0 >>>> + ARM_BE8(rev16 ip, ip) >>>> strh ip, [r7, #2] >>>> + ldrheq ip, [r7] >>>> + biceq ip, #0x20 >>>> + orreq ip, ip, r0, lsr #16 >>>> + strheq ip, [r7] >>> There are new halfword accesses here without any conditional revs. >> Yes, I missed this one. >> >>>> + #ifdef CONFIG_CPU_ENDIAN_BE8 >>>> + @ in BE8, we load data in BE, but instructions still in LE >>>> + bic ip, ip, #0xff000000 >>>> - orr ip, ip, r6, lsl#24 >>>> ++ tst ip, #0x000f0000 @ check the rotation field >>> Since that orr with shift has been removed, I think the masks for the BE >>> case are now incorrect... >>> >>>> ++ orrne ip, ip, r6, lsl #24 @ mask in offset bits 31-24 >>>> ++ biceq ip, ip, #0x00004000 @ clear bit 22 >>>> ++ orreq ip, ip, r0, lsl #24 @ mask in offset bits 7-0 >> Actually, look closer. It became the orrne here. >> >>>> + #else >>>> bic ip, ip, #0x000000ff >>>> - orr ip, ip, r6 @ mask in offset bits 31-24 >>>> + tst ip, #0xf00 @ check the rotation field >>>> + orrne ip, ip, r6 @ mask in offset bits 31-24 >>>> + biceq ip, ip, #0x400000 @ clear bit 22 >>> ...which seems to be confirmed by the updated LE code (everything is off >>> by a byte). >> The LE code was left unaltered from Santosh's patch, so that should be >> correct. I just did an endian conversion to the BE case. >> >>> Somebody should probably sit down with the conflicting patch and port the BE >>> changes over. I think the relevant patch is "ARM: mm: Correct virt_to_phys >>> patching for 64 bit physical addresses". In fact, looking at *that* patch, >>> it's *also* broken for BE! It adds the following to head.S: >>> >>> +#ifdef __ARMEB_ >>> +#define LOW_OFFSET 0x4 >>> +#define HIGH_OFFSET 0x0 >>> +#else >>> +#define LOW_OFFSET 0x0 >>> +#define HIGH_OFFSET 0x4 >>> +#endif >>> >>> (spot the missing underscore). >> Yep, well spotted. >> >> Well, we have some time to get this all fixed, so I'm going to drop >> Ben's tree. I think we need to first commit a patch to fix the error >> in Santosh's patch. > Sorry, I will send a patch fix this missing underscore bug. > > Regards, > Sricharan diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 2b3e981..8b03c2c 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -662,6 +662,7 @@ ARM_BE8(rev ip, ip) #endif ENDPROC(__fixup_a_pv_table) + .align 3: .long __pv_offset ENTRY(fixup_pv_table)