From patchwork Thu Dec 20 18:45:24 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 1900791 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id BB04CDF23A for ; Thu, 20 Dec 2012 18:52:28 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1Tll7c-0005cF-2y; Thu, 20 Dec 2012 18:45:32 +0000 Received: from mail-ee0-f45.google.com ([74.125.83.45]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1Tll7Y-0005bv-Oe for linux-arm-kernel@lists.infradead.org; Thu, 20 Dec 2012 18:45:29 +0000 Received: by mail-ee0-f45.google.com with SMTP id d49so1917759eek.18 for ; Thu, 20 Dec 2012 10:45:25 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:x-gm-message-state; bh=yXx/3x5rcshe0V2tKuefTK5+2BJX9lekdGuYM1sOAro=; b=DCjWCU9xSTjHWUlbIt0jRWD7+sh9Miit9kIHjDO1IcgHZ5yzWw3mmtQzkwmy+OsKpc S+SBeL4svX9cyl58DpbgXvJcFRQPtQ88xQf1WHAPFfDTSvKNE7Tp8IVZv5fusWiODtgI iyBvbxJFHUkDMYtfxaEwQkJaeMz7lfJh9T0oRGi+ta6FBASyJPXnrJTb1ciibBkBdI6Y ahAMC06AarnF4QVWhmQLOoRqUT74zs3M31c49hnbOQ9tHELaj1fgifayi9mgWwo93ZBZ YHyvNyeOdmRKk4gQF4oDgsmIpsQgxRl4+NblUpVPrPG9BGLIY3AHRBErQZuBHKcP7ZHx PFWw== MIME-Version: 1.0 Received: by 10.14.194.195 with SMTP id m43mr25143587een.44.1356029125079; Thu, 20 Dec 2012 10:45:25 -0800 (PST) Received: by 10.223.96.4 with HTTP; Thu, 20 Dec 2012 10:45:24 -0800 (PST) In-Reply-To: References: <1350392786-29191-1-git-send-email-linus.walleij@stericsson.com> <507D61E7.2080704@gmail.com> Date: Thu, 20 Dec 2012 19:45:24 +0100 Message-ID: Subject: Re: [PATCH] ARM: VIC: use irq_domain_add_simple() From: Linus Walleij To: Grant Likely X-Gm-Message-State: ALoCoQmNUsjMcIINQRQ85YXqQ5GhUyZJvBrhU4JBoquJnsgWpmmmgtv2bKKTuIPdyD/pPt4llhnj X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121220_134528_992866_A375B850 X-CRM114-Status: GOOD ( 23.12 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [74.125.83.45 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Anmar Oueja , Rob Herring , Russell King - ARM Linux , Linus Walleij , "linux-arm-kernel@lists.infradead.org" X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org On Wed, Dec 19, 2012 at 12:34 AM, Grant Likely wrote: > It looks to me like the below patch breaks versatile because it makes > it try to register a linear irq_domain instead of the legacy one that > it needs. Here are the relevant commits: > > 07c9249f1: "ARM: 7554/1: VIC: use irq_domain_add_simple()" > 946c59a08: "ARM: vic: fix build warning caused by previous commit" > > I'm working on getting it properly sorted out (and more importantly > *simplified*), but in the mean time I think the above two commits need > to be reverted. Reverting them on my tree fixes booting for me. Isn't that a bit violent, can't we just fix the real bug? Does the below patch work for you, it does two things: 1) Bump all Versatile IRQs to offset at 32, because it is using IRQ 0 which is NO_IRQ and illegal anyway so it's anyway a bug that should be fixed. 2) Make sure we call irq_create_mapping() if the start IRQ is anyway 0, as in the device tree case, and make sure to actually pass zero in that case. The initial patch set used negative IRQ as an indicator that the linear domain should be used and not descriptors allocated, but as that require changing a lot of singatures to signed int and since IRQ 0 is now illegal anyway, I let zero signify linear. Sorry for leftover mistakes like this... I'll mail them out as separate patches too, and submit to Russell's tracker if they fix the problem. Yours, Linus Walleij Acked-by: Grant Likely diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c index e4df17c..8f324b9 100644 --- a/arch/arm/common/vic.c +++ b/arch/arm/common/vic.c @@ -206,6 +206,7 @@ static void __init vic_register(void __iomem *base, unsigned int irq, struct device_node *node) { struct vic_device *v; + int i; if (vic_id >= ARRAY_SIZE(vic_devices)) { printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__); @@ -220,6 +221,10 @@ static void __init vic_register(void __iomem *base, unsigned int irq, vic_id++; v->domain = irq_domain_add_simple(node, fls(valid_sources), irq, &vic_irqdomain_ops, v); + /* create an IRQ mapping for each valid IRQ */ + for (i = 0; i < fls(valid_sources); i++) + if (valid_sources & (1 << i)) + irq_create_mapping(v->domain, i); } static void vic_ack_irq(struct irq_data *d) @@ -416,9 +421,9 @@ int __init vic_of_init(struct device_node *node, struct device_node *parent) return -EIO; /* - * Passing -1 as first IRQ makes the simple domain allocate descriptors + * Passing 0 as first IRQ makes the simple domain allocate descriptors */ - __vic_init(regs, -1, ~0, ~0, node); + __vic_init(regs, 0, ~0, ~0, node); return 0; } diff --git a/arch/arm/mach-versatile/include/mach/irqs.h b/arch/arm/mach-versatile/include/mach/irqs.h index bf44c61..0fd771c 100644 --- a/arch/arm/mach-versatile/include/mach/irqs.h +++ b/arch/arm/mach-versatile/include/mach/irqs.h @@ -25,7 +25,7 @@ * IRQ interrupts definitions are the same as the INT definitions * held within platform.h */ -#define IRQ_VIC_START 0 +#define IRQ_VIC_START 32 #define IRQ_WDOGINT (IRQ_VIC_START + INT_WDOGINT) #define IRQ_SOFTINT (IRQ_VIC_START + INT_SOFTINT) #define IRQ_COMMRx (IRQ_VIC_START + INT_COMMRx) @@ -100,7 +100,7 @@ /* * Secondary interrupt controller */ -#define IRQ_SIC_START 32 +#define IRQ_SIC_START 64 #define IRQ_SIC_MMCI0B (IRQ_SIC_START + SIC_INT_MMCI0B) #define IRQ_SIC_MMCI1B (IRQ_SIC_START + SIC_INT_MMCI1B) #define IRQ_SIC_KMI0 (IRQ_SIC_START + SIC_INT_KMI0) @@ -120,7 +120,7 @@ #define IRQ_SIC_PCI1 (IRQ_SIC_START + SIC_INT_PCI1) #define IRQ_SIC_PCI2 (IRQ_SIC_START + SIC_INT_PCI2) #define IRQ_SIC_PCI3 (IRQ_SIC_START + SIC_INT_PCI3) -#define IRQ_SIC_END 63 +#define IRQ_SIC_END 95 #define IRQ_GPIO0_START (IRQ_SIC_END + 1) #define IRQ_GPIO0_END (IRQ_GPIO0_START + 31)