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Mon, 16 Dec 2013 18:37:14 -0800 (PST) Received: by 10.60.36.166 with HTTP; Mon, 16 Dec 2013 18:37:14 -0800 (PST) In-Reply-To: References: Date: Mon, 16 Dec 2013 18:37:14 -0800 Message-ID: Subject: Re: [PATCH 1/3]: Support cpu frequency scaling and power management for iMX6SL From: John Tobias To: linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org, Shawn Guo , Fabio Estevam , Chris Ball X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131216_213740_147078_82BE2232 X-CRM114-Status: GOOD ( 10.98 ) X-Spam-Score: -2.7 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Need some correction: From: John Tobias }; On Mon, Dec 16, 2013 at 5:40 PM, John Tobias wrote: > iMX6SL device tree doesn't have a configuration settings to enable the > frequency scaling and power management. > > From: John Tobias > > > diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi > index 28558f1..0ad2f6a 100644 > --- a/arch/arm/boot/dts/imx6sl.dtsi > +++ b/arch/arm/boot/dts/imx6sl.dtsi > @@ -38,6 +38,19 @@ > device_type = "cpu"; > reg = <0x0>; > next-level-cache = <&L2>; > + operating-points = < > + /* kHz uV */ > + 1000000 1275000 > + 792000 1150000 > + >; > + clock-latency = <61036>; /* two CLK32 periods */ > + clocks = <&clks IMX6SL_CLK_ARM>, <&clks > IMX6SL_CLK_PLL2_PFD2>, <&clks IMX6SL_CLK_STEP>, > + <&clks IMX6SL_CLK_PLL1_SW>, <&clks > IMX6SL_CLK_PLL1_SYS>; > + clock-names = "arm", "pll2_pfd2_396m", "step", > + "pll1_sw", "pll1_sys"; > + arm-supply = <®_arm>; > + pu-supply = <®_pu>; > + soc-supply = <®_soc>; > }; > }; diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 28558f1..6035e7e 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -38,6 +38,21 @@ device_type = "cpu"; reg = <0x0>; next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 1000000 1275000 + 996000 1250000 + 792000 1150000 + 396000 950000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>, <&clks IMX6SL_CLK_STEP>, + <&clks IMX6SL_CLK_PLL1_SW>, <&clks IMX6SL_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; };