From patchwork Mon Jun 9 20:35:10 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 4323611 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 84121BEEAA for ; Mon, 9 Jun 2014 20:37:45 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B8D33201BC for ; Mon, 9 Jun 2014 20:37:44 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EA8052009C for ; Mon, 9 Jun 2014 20:37:43 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Wu6I2-00037R-Eg; Mon, 09 Jun 2014 20:35:34 +0000 Received: from mail-ve0-x22f.google.com ([2607:f8b0:400c:c01::22f]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Wu6I0-0002k8-2Q for linux-arm-kernel@lists.infradead.org; Mon, 09 Jun 2014 20:35:32 +0000 Received: by mail-ve0-f175.google.com with SMTP id us18so4972650veb.34 for ; Mon, 09 Jun 2014 13:35:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=EKYUD9DIG5xu9XIzQcGR6gpntu2CCZQk4o85052xE0Y=; b=mgXELLBejyMhfFzASss9IpTZu55GY0LA81KJ+EQJKW3lFYJW1JF8JaMgzG/8+OqFcM mQ8Rk3UUsQuOoZE7VTfyRUXFleTuwyFbk+YPw2QFnraKDfEzyCV22odAAgxRNUgVlEJu KN2I7CMd7dEoLmf7AmwsK5F55sCquUkF85mgUzwzvvzlTL44EbG6paC3fSsjQdI8DoZr 8xuCvfc2Ew9eT5gm0r/aHxR9muWRRHp+44Jb/pXK8EShQLiD9Y6zMrkSGrqoguPeKMSU LlOkq+8UkqRhhu6qHB0cbyAj2rRwCFI3y0ww9sPHNbRMnfPQGMt3xDf+5A9QpQVho1zq vq9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc:content-type; bh=EKYUD9DIG5xu9XIzQcGR6gpntu2CCZQk4o85052xE0Y=; b=djeL6liy3b1AFgOmH4mvHFvaFNem7xCa3JHdbRYkqNetN4pY20G1O2qdanIFSYC9j7 yN0OE8nrp2N5dQ1GjLn5yiOMk4pWLjSHJ3kJvHI/n/40HrtOKzrPRQMqXmuHxI/wn3cF /1jCZfybFIUZB7BlqHjZZ2UcvAj4Crpq+zIb7HEpD3xTJLuJb1jonTe8+B2u7BnyO+zb 5J/PzdZwF6fKNgQEr59GMV8jueDY+q4uUS26dkg6mpEUrOE/9qqoKcz/TpCFjXthApBl t1wEFUrSoCLiV2IiHnGN8678eXN6UDA1jy6OkbOlzMlmVaEMghJ+Mv7NdENuPc0ae/+R v/Sg== X-Gm-Message-State: ALoCoQlggOD8sfK5NdFNytxpXgcvIKaRBGE8B4EZsEpkLhqnpq0+vA7QHn5bQkUmLck76LnvUojz MIME-Version: 1.0 X-Received: by 10.221.42.135 with SMTP id ty7mr28146642vcb.14.1402346110224; Mon, 09 Jun 2014 13:35:10 -0700 (PDT) Received: by 10.52.174.234 with HTTP; Mon, 9 Jun 2014 13:35:10 -0700 (PDT) In-Reply-To: <7hoay1rfp4.fsf@paris.lan> References: <539145B4.5000200@gmail.com> <7hoay1rfp4.fsf@paris.lan> Date: Mon, 9 Jun 2014 13:35:10 -0700 Message-ID: Subject: Re: Problems booting exynos5420 with >1 CPU From: Doug Anderson To: Kevin Hilman , Nicolas Pitre X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140609_133532_195449_BF2369DC X-CRM114-Status: GOOD ( 22.67 ) X-Spam-Score: -0.8 (/) Cc: Abhilash Kesavan , Tushar Behera , "Turquette, Mike" , linux-samsung-soc , Thomas Abraham , Arun Kumar , Olof Johansson , Sonny Rao , Javier Martinez Canillas , linux-arm-kernel X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.4 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Kevin and Nicolas, On Mon, Jun 9, 2014 at 1:27 PM, Kevin Hilman wrote: > Nicolas Pitre writes: > >> On Sat, 7 Jun 2014, Abhilash Kesavan wrote: >> >>> Hi Nicolas, >>> >>> The first man of the incoming cluster enables its snoops via the >>> power_up_setup function. During secondary boot-up, this does not occur >>> for the boot cluster. Hence, I enable the snoops for the boot cluster >>> as a one-time setup from the u-boot prompt. After secondary boot-up >>> there is no modification that I do. >> >> OK that's good. >> >>> Where should this be ideally done ? >> >> If I remember correctly, the CCI can be safely activated only when the >> cache is disabled. So that means the CCI should ideally be turned on >> for the boot cluster (and *only* for the boot CPU) by the bootloader. >> >> Now... If you _really_ prefer to do it from the kernel to avoid >> difficulties with bootloader updates, then it should be possible to do >> it from the kernel by temporarily turning the cache off. This is not a >> small thing but the MCPM infrastructure can be leveraged. Here's what I >> tried on a TC2 which might just work for you as well: > > FWIW, I dropped the u-boot hack I was using to enable CCI and tested > this patch (with a cut/paste of the TC2 specific stuff into > mach-exynos/mcpm-exynos.c) along with Doug's patch[1] and > and confirm that all 8 cores boot up on the Chromebook2 using linux-next. > > Kevin > > [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2014-June/262440.html Agreed. Nicolas's patch plus the copy/paste to exynos made things boot for me, too. -Doug --- Reference of the copy/paste to exynos (though gmail is munging my tabs): diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c index ace0ed6..218b9ff 100644 --- a/arch/arm/mach-exynos/mcpm-exynos.c +++ b/arch/arm/mach-exynos/mcpm-exynos.c @@ -295,6 +295,25 @@ static const struct of_device_id exynos_dt_mcpm_match[] = { {}, }; +int mcpm_loopback(void (*cache_disable)(void)); +static void exynos_cache_down(void) +{ + pr_warn("exynos: disabling cache\n"); + if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A15) { + /* + * On the Cortex-A15 we need to disable + * L2 prefetching before flushing the cache. + */ + asm volatile( + "mcr p15, 1, %0, c15, c0, 3 \n\t" + "isb \n\t" + "dsb " + : : "r" (0x400) ); + } + v7_exit_coherency_flush(all); + cci_disable_port_by_cpu(read_cpuid_mpidr()); +} + static int __init exynos_mcpm_init(void) { struct device_node *node; @@ -336,6 +355,7 @@ static int __init exynos_mcpm_init(void) iounmap(ns_sram_base_addr); return ret; } + BUG_ON(mcpm_loopback(exynos_cache_down) != 0); mcpm_smp_set_ops();