From patchwork Wed Sep 12 15:19:16 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Ramesh" X-Patchwork-Id: 1445021 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (unknown [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 6DB64DF28C for ; Wed, 12 Sep 2012 15:42:54 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TBoir-0006qL-CA; Wed, 12 Sep 2012 15:19:26 +0000 Received: from na3sys009aog110.obsmtp.com ([74.125.149.203]) by merlin.infradead.org with smtps (Exim 4.76 #1 (Red Hat Linux)) id 1TBoik-0006oR-UB for linux-arm-kernel@lists.infradead.org; Wed, 12 Sep 2012 15:19:20 +0000 Received: from mail-pb0-f71.google.com ([209.85.160.71]) (using TLSv1) by na3sys009aob110.postini.com ([74.125.148.12]) with SMTP ID DSNKUFCn9d8EkXhyu7M4cFtC+g18OJkQ+uyt@postini.com; Wed, 12 Sep 2012 08:19:18 PDT Received: by pbbrr4 with SMTP id rr4so3803018pbb.6 for ; Wed, 12 Sep 2012 08:19:16 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:date:message-id:subject:from:to:cc:content-type :x-gm-message-state; bh=GQOrrhwPNBc+iIfRoOfrqQzssWi7pxKojfujKV0acxA=; b=Bv6JUFtvJObSNN+NolJk+/fg2T/9gwbC+3hfaS4fQ9qGmNBkAbwauUjuY9/cNoMpO0 sq/ghjXMg9/RKdohzQDEiYY/0FMhFB2ey9h9sDvu14uYkiBh2aTYvNucgif3Bha4G+5p /kEPDbONqEgHlRTyWmviDjJ8IrmTWepKphexpPI6tNwjk/dO3ssZ+LfzVHnjT76CpZos v/3scHZrxLhd/IUPPe0Q8JElklJWBf4Cnkt2wJt7c02DfKXjxcttxbJYEKMmE/5DY13c hWDSiQvOhnknXRs5cbysb6dqtYVRIMB6f1BPeZmE/zaPSlcFe5FkFVBescz1brB2ia62 JgGQ== Received: by 10.66.80.98 with SMTP id q2mr22023322pax.29.1347463156594; Wed, 12 Sep 2012 08:19:16 -0700 (PDT) MIME-Version: 1.0 Received: by 10.66.80.98 with SMTP id q2mr22023311pax.29.1347463156464; Wed, 12 Sep 2012 08:19:16 -0700 (PDT) Received: by 10.66.73.10 with HTTP; Wed, 12 Sep 2012 08:19:16 -0700 (PDT) Date: Wed, 12 Sep 2012 20:49:16 +0530 Message-ID: Subject: [PATCH v5 2/2] OMAP:IOMMU:flush L1 and L2 caches From: "Gupta, Ramesh" To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org X-Gm-Message-State: ALoCoQkax77GdcungJXs7DAWlPnICAWmledR0h5+Ak8EgIu3S1+2PO38ctd2Z3ntKNPoCoDiUYL1O3/ugKDDoJDuphkmOm0LQdhEYXBMgjNvQ8enRqjI3AEpk1rv1wyfvOoV1i6Cd9blmQc75MAxoCNdi8C4Q2Vld2OrYydORgQsTtGcjcASzcb5nfbelN+fh8A65trJ9K4W X-Spam-Note: CRM114 invocation failed X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [74.125.149.203 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: tony@atomide.com, Russell King - ARM Linux X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From d78ddb5b0dffed3fd77e6e010735e869ea41b02f Mon Sep 17 00:00:00 2001 From: Ramesh Gupta G Date: Wed, 12 Sep 2012 19:05:29 +0530 Subject: [PATCH v5 2/2] OMAP:IOMMU:flush L1 and L2 caches OMAP IOMMU need to make sure that data in the L1 and L2 caches is visible to the MMU hardware whenever the pagetables are updated. The current code only takes care of L1 cache using assembly. Added code to handle this using a new L1 cache maintenance function and the outer cache function. Thanks to the RMK's suggestions. Signed-off-by: Ramesh Gupta G --- drivers/iommu/omap-iommu.c | 41 +++++++++++++++++++---------------------- 1 files changed, 19 insertions(+), 22 deletions(-) } else { @@ -544,7 +541,7 @@ static int iopgd_alloc_section(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) } *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION; - flush_iopgd_range(iopgd, iopgd); + flush_iopgd_range(iopgd, sizeof(*iopgd)); return 0; } @@ -561,7 +558,7 @@ static int iopgd_alloc_super(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) for (i = 0; i < 16; i++) *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER; - flush_iopgd_range(iopgd, iopgd + 15); + flush_iopgd_range(iopgd, sizeof(*iopgd) * 16); return 0; } @@ -574,7 +571,7 @@ static int iopte_alloc_page(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) return PTR_ERR(iopte); *iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL; - flush_iopte_range(iopte, iopte); + flush_iopte_range(iopte, sizeof(*iopte)); dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n", __func__, da, pa, iopte, *iopte); @@ -599,7 +596,7 @@ static int iopte_alloc_large(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) for (i = 0; i < 16; i++) *(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE; - flush_iopte_range(iopte, iopte + 15); + flush_iopte_range(iopte, sizeof(*iopte) * 16); return 0; } @@ -702,7 +699,7 @@ static size_t iopgtable_clear_entry_core(struct omap_iommu *obj, u32 da) } bytes *= nent; memset(iopte, 0, nent * sizeof(*iopte)); - flush_iopte_range(iopte, iopte + (nent - 1) * sizeof(*iopte)); + flush_iopte_range(iopte, iopte + (nent) * sizeof(*iopte)); /* * do table walk to check if this table is necessary or not @@ -724,7 +721,7 @@ static size_t iopgtable_clear_entry_core(struct omap_iommu *obj, u32 da) bytes *= nent; } memset(iopgd, 0, nent * sizeof(*iopgd)); - flush_iopgd_range(iopgd, iopgd + (nent - 1) * sizeof(*iopgd)); + flush_iopgd_range(iopgd, iopgd + (nent) * sizeof(*iopgd)); out: return bytes; } @@ -768,7 +765,7 @@ static void iopgtable_clear_entry_all(struct omap_iommu *obj) iopte_free(iopte_offset(iopgd, 0)); *iopgd = 0; - flush_iopgd_range(iopgd, iopgd); + flush_iopgd_range(iopgd, sizeof(*iopgd)); } flush_iotlb_all(obj); diff --git a/drivers/iommu/omap-iommu.c b/drivers/iommu/omap-iommu.c index d0b1234..8f61ef9 100644 --- a/drivers/iommu/omap-iommu.c +++ b/drivers/iommu/omap-iommu.c @@ -469,24 +469,21 @@ EXPORT_SYMBOL_GPL(omap_foreach_iommu_device); /* * H/W pagetable operations */ -static void flush_iopgd_range(u32 *first, u32 *last) +static void flush_iopgd_range(u32 *first, size_t size) { - /* FIXME: L2 cache should be taken care of if it exists */ - do { - asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pgd" - : : "r" (first)); - first += L1_CACHE_BYTES / sizeof(*first); - } while (first <= last); + phys_addr_t phys = virt_to_phys(first); + + iommu_flush_area(first, size); + outer_flush_range(phys, phys + size); } -static void flush_iopte_range(u32 *first, u32 *last) +static void flush_iopte_range(u32 *first, size_t size) + { - /* FIXME: L2 cache should be taken care of if it exists */ - do { - asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pte" - : : "r" (first)); - first += L1_CACHE_BYTES / sizeof(*first); - } while (first <= last); + phys_addr_t phys = virt_to_phys(first); + + iommu_flush_area(first, size); + outer_flush_range(phys, phys + size); } static void iopte_free(u32 *iopte) @@ -515,7 +512,7 @@ static u32 *iopte_alloc(struct omap_iommu *obj, u32 *iopgd, u32 da) return ERR_PTR(-ENOMEM); *iopgd = virt_to_phys(iopte) | IOPGD_TABLE; - flush_iopgd_range(iopgd, iopgd); + flush_iopgd_range(iopgd, sizeof(*iopgd)); dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte);