From patchwork Wed Jul 6 03:14:57 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: heechul Yun X-Patchwork-Id: 948342 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter1.kernel.org (8.14.4/8.14.4) with ESMTP id p663i9sg010636 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Wed, 6 Jul 2011 03:44:29 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QeIzI-0007ak-Vz; Wed, 06 Jul 2011 03:41:21 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QeIzI-0006eM-6a; Wed, 06 Jul 2011 03:41:20 +0000 Received: from mail-yx0-f177.google.com ([209.85.213.177]) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QeIxj-0006B3-SS for linux-arm-kernel@lists.infradead.org; Wed, 06 Jul 2011 03:39:44 +0000 Received: by yxj20 with SMTP id 20so1406307yxj.36 for ; Tue, 05 Jul 2011 20:39:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:sender:date:x-google-sender-auth:message-id:subject :from:to:cc:content-type; bh=us2BCG8t0LJv36jx6OF7XEAWuwA92c+SA06z4qF+418=; b=P8nYs0kucX9eESph3mvpCS68YtCVVI26dcmXOOIYqPo9Z7GCMhz+h1ATrEbMMrslV9 rtFS7ZnL0xeMp9UxzlgJhSYMLJ2Zyu9Ax2rZDRRCaZecqi10FrXT5v1zRNIEiOiI1CE9 Aj6dIk/ygEVc/kMu7YbgOMcTG/DPrOmBMqVZk= MIME-Version: 1.0 Received: by 10.236.115.168 with SMTP id e28mr9743706yhh.334.1309922097801; Tue, 05 Jul 2011 20:14:57 -0700 (PDT) Received: by 10.236.61.35 with HTTP; Tue, 5 Jul 2011 20:14:57 -0700 (PDT) Date: Tue, 5 Jul 2011 20:14:57 -0700 X-Google-Sender-Auth: KtK92N5M3muRVup8jDJHaBxBcJw Message-ID: Subject: A few other cache related optimizations for Cortex-A9. From: heechul Yun To: Catalin Marinas , Russell King - ARM Linux X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110705_233944_115784_EC187782 X-CRM114-Status: GOOD ( 12.15 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.213.177 listed in list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (heechul.yun[at]gmail.com) 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: "linux-arm-kernel@lists.infradead.org" X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Wed, 06 Jul 2011 03:44:29 +0000 (UTC) I found a few other places which, I believe, are not necessary for Cortex-A9. Creating page tables also do not need to clean cache-line because of the same reason as above. This patch improves lmbench3 (fork/exec/shell) performance by 10%~20% in my test. I think above two patches work for least Cortex-A9 although I am not sure the use of CONFIG_CPU_CACHE_V7 is appropriate. Thanks diff --git a/arch/arm/mm/copypage-v6.c b/arch/arm/mm/copypage-v6.c index bdba6c6..6d5a847 100644 --- a/arch/arm/mm/copypage-v6.c +++ b/arch/arm/mm/copypage-v6.c @@ -41,7 +41,9 @@ static void v6_copy_user_highpage_nonaliasing(struct page *to, kfrom = kmap_atomic(from, KM_USER0); kto = kmap_atomic(to, KM_USER1); copy_page(kto, kfrom); +#ifndef CONFIG_CPU_CACHE_V7 __cpuc_flush_dcache_area(kto, PAGE_SIZE); +#endif kunmap_atomic(kto, KM_USER1); kunmap_atomic(kfrom, KM_USER0); } On handling COW page fault, the above function is called to copy the page content of the parent to a newly allocate page frame for the child. Again, since D cache of A9 is PIPT, we do not need to flush the page as in x86. This modification improves lmbench (fork/exec/shell) performance by 4-6%. diff --git a/arch/arm/include/asm/pgalloc.h b/arch/arm/include/asm/pgalloc.h index b12cc98..bff9858 100644 --- a/arch/arm/include/asm/pgalloc.h +++ b/arch/arm/include/asm/pgalloc.h @@ -61,7 +61,9 @@ pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr) pte = (pte_t *)__get_free_page(PGALLOC_GFP); if (pte) { +#if !CONFIG_CPU_CACHE_V7 clean_dcache_area(pte, sizeof(pte_t) * PTRS_PER_PTE); +#endif pte += PTRS_PER_PTE; } @@ -81,7 +83,9 @@ pte_alloc_one(struct mm_struct *mm, unsigned long addr) if (pte) { if (!PageHighMem(pte)) { void *page = page_address(pte); +#if !CONFIG_CPU_CACHE_V7 clean_dcache_area(page, sizeof(pte_t) * PTRS_PER_PTE); +#endif } pgtable_page_ctor(pte); } diff --git a/arch/arm/mm/pgd.c b/arch/arm/mm/pgd.c index be5f58e..343df1b 100644 --- a/arch/arm/mm/pgd.c +++ b/arch/arm/mm/pgd.c @@ -41,8 +41,9 @@ pgd_t *get_pgd_slow(struct mm_struct *mm) memcpy(new_pgd + FIRST_KERNEL_PGD_NR, init_pgd + FIRST_KERNEL_PGD_NR, (PTRS_PER_PGD - FIRST_KERNEL_PGD_NR) * sizeof(pgd_t)); +#if !CONFIG_CPU_CACHE_V7 clean_dcache_area(new_pgd, PTRS_PER_PGD * sizeof(pgd_t)); - +#endif if (!vectors_high()) { /* * On ARM, first page must always be allocated since it