From patchwork Mon Aug 1 13:10:29 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Francois Moine X-Patchwork-Id: 9254405 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 2C4A96077C for ; Mon, 1 Aug 2016 13:36:38 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1D36420499 for ; Mon, 1 Aug 2016 13:36:38 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1213A28402; Mon, 1 Aug 2016 13:36:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00,FREEMAIL_FROM, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id AC8C120499 for ; Mon, 1 Aug 2016 13:36:37 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bUDND-0000pR-65; Mon, 01 Aug 2016 13:35:15 +0000 Received: from smtp4-g21.free.fr ([2a01:e0c:1:1599::13]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1bUDMS-0000h5-4Y for linux-arm-kernel@lists.infradead.org; Mon, 01 Aug 2016 13:34:32 +0000 Received: from localhost (unknown [IPv6:2a01:e35:2f5c:9de0:4641:5d4e:ba5d:2fa9]) by smtp4-g21.free.fr (Postfix) with ESMTP id A4F6B19F58A; Mon, 1 Aug 2016 15:36:41 +0200 (CEST) X-Mailbox-Line: From 05567615bb5739aa298d122aeeddd808a64a7272 Mon Sep 17 00:00:00 2001 From: Jean-Francois Moine Date: Mon, 1 Aug 2016 15:10:29 +0200 Subject: [PATCH v2] mmc: sunxi: Handle the 'New Timings' To: Ulf Hansson , Maxime Ripard , Chen-Yu Tsai X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160801_063428_330723_D64A70B5 X-CRM114-Status: GOOD ( 13.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-sunxi@googlegroups.com, linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Message-ID: Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Some MMC devices as mmc2 in the A83T or mmc1 and mmc2 in the H3 have a 'New Timings' mode. Set this capacity in the DT and use it when possible. Signed-off-by: Jean-Francois Moine --- I don't know if this mode works or is needed at 25MHz. --- Documentation/devicetree/bindings/mmc/sunxi-mmc.txt | 1 + drivers/mmc/host/sunxi-mmc.c | 21 +++++++++++++++++++-- 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt index 4bf41d8..a541bf4 100644 --- a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt +++ b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt @@ -19,6 +19,7 @@ Optional properties: - reset-names : must contain "ahb" - for cd, bus-width and additional generic mmc parameters please refer to mmc.txt within this directory + - allwinner,new-timings: the controller may accept the "New Timings" mode Examples: - Within .dtsi: diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c index 2ee4c21..98922b5 100644 --- a/drivers/mmc/host/sunxi-mmc.c +++ b/drivers/mmc/host/sunxi-mmc.c @@ -64,6 +64,7 @@ #define SDXC_REG_CBCR (0x48) /* SMC CIU Byte Count Register */ #define SDXC_REG_BBCR (0x4C) /* SMC BIU Byte Count Register */ #define SDXC_REG_DBGC (0x50) /* SMC Debug Enable Register */ +#define SDXC_REG_NTSR (0x5c) /* SMC NewTiming Set Register */ #define SDXC_REG_HWRST (0x78) /* SMC Card Hardware Reset for Register */ #define SDXC_REG_DMAC (0x80) /* SMC IDMAC Control Register */ #define SDXC_REG_DLBA (0x84) /* SMC IDMAC Descriptor List Base Addre */ @@ -171,6 +172,9 @@ #define SDXC_SEND_AUTO_STOPCCSD BIT(9) #define SDXC_CEATA_DEV_IRQ_ENABLE BIT(10) +/* NewTiming Set Register */ +#define SDXC_NEWMODE_ENABLE BIT(31) + /* IDMA controller bus mod bit field */ #define SDXC_IDMAC_SOFT_RESET BIT(0) #define SDXC_IDMAC_FIX_BURST BIT(1) @@ -261,6 +265,9 @@ struct sunxi_mmc_host { /* vqmmc */ bool vqmmc_enabled; + + /* misc */ + bool new_timings; /* new timings capable */ }; static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host) @@ -715,8 +722,13 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host, return -EINVAL; } - clk_set_phase(host->clk_sample, sclk_dly); - clk_set_phase(host->clk_output, oclk_dly); + if (host->new_timings && rate >= 50000000) { + mmc_writel(host, REG_NTSR, + mmc_readl(host, REG_NTSR) | SDXC_NEWMODE_ENABLE); + } else { + clk_set_phase(host->clk_sample, sclk_dly); + clk_set_phase(host->clk_output, oclk_dly); + } return sunxi_mmc_oclk_onoff(host, 1); } @@ -1133,12 +1145,17 @@ static int sunxi_mmc_probe(struct platform_device *pdev) if (ret) goto error_free_dma; + if (pdev->dev.of_node && + of_property_read_bool(pdev->dev.of_node, "allwinner,new-timings")) + host->new_timings = true; + ret = mmc_add_host(mmc); if (ret) goto error_free_dma; dev_info(&pdev->dev, "base:0x%p irq:%u\n", host->reg_base, host->irq); platform_set_drvdata(pdev, mmc); + return 0; error_free_dma: