From patchwork Thu Jun 11 14:32:42 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabriele Paoloni X-Patchwork-Id: 6589001 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 469D69F2F4 for ; Thu, 11 Jun 2015 14:36:36 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C49F9205DC for ; Thu, 11 Jun 2015 14:36:32 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7DF0020638 for ; Thu, 11 Jun 2015 14:36:25 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Z33Y9-0005Do-AY; Thu, 11 Jun 2015 14:33:45 +0000 Received: from lhrrgout.huawei.com ([194.213.3.17]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Z33Y2-00054J-Ig for linux-arm-kernel@lists.infradead.org; Thu, 11 Jun 2015 14:33:42 +0000 Received: from 172.18.7.190 (EHLO lhreml401-hub.china.huawei.com) ([172.18.7.190]) by lhrrg02-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id BTR33999; Thu, 11 Jun 2015 14:32:54 +0000 (GMT) Received: from LHREML505-MBX.china.huawei.com ([169.254.1.51]) by lhreml401-hub.china.huawei.com ([10.201.5.240]) with mapi id 14.03.0158.001; Thu, 11 Jun 2015 15:32:42 +0100 From: Gabriele Paoloni To: "Wangzhou (B)" Subject: RE: [PATCH v2 2/4] PCI: designware: Add ARM64 support Thread-Topic: [PATCH v2 2/4] PCI: designware: Add ARM64 support Thread-Index: AQHQndd31KF7tmLYzUykT94o1PxjdZ2cRd2AgAE8JACABnyhgIABxM8wgAEDbQCAAKOzYA== Date: Thu, 11 Jun 2015 14:32:42 +0000 Message-ID: References: <1433320542-49576-1-git-send-email-wangzhou1@hisilicon.com> <1433320542-49576-3-git-send-email-wangzhou1@hisilicon.com> <5570507F.4030704@arm.com> <557159B2.9090103@hisilicon.com> <20150609111507.GB20182@red-moon> <55792032.2080903@hisilicon.com> In-Reply-To: <55792032.2080903@hisilicon.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.122.142.33] MIME-Version: 1.0 X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150611_073339_430393_4846BBE7 X-CRM114-Status: GOOD ( 21.28 ) X-Spam-Score: -2.3 (--) Cc: Zhudacai , Pratyush Anand , Lorenzo Pieralisi , Arnd Bergmann , "devicetree@vger.kernel.org" , "linux-pci@vger.kernel.org" , Jingoo Han , Liviu Dudau , Yuanzhichang , zhangjukuo , James Morse , qiuzhenfa , Bjorn Helgaas , "fabrice.gasnier@st.com" , "Liguozhu \(Kenneth\)" , "linux-arm-kernel@lists.infradead.org" X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Hi Zhou Wang I apologize, I made a mistake as I didn't rebase the patch on the latest Kernel (where I was convinced I did), my bad. The patch below is based on v4.1-rc7 It passes checkpatch and compiles OK Cheers Gab ------------------------------------------- ------------------------------------------- This patch is a rework of "[PATCH v2 2/4] PCI: designware: Add ARM64 support" from Zhou Wang. The intention is to complete the unification between ARM and ARM64 now that the dependency on arch/arm/kernel/bios32.c is gone. I have also included the rework asked by James Morse: io_base declared as resource_size_t It compiles fine on ARCH arm and arm64 on Linux 4.1-rc7. It needs to be tested. Signed-off-by: Gabriele Paoloni --- drivers/pci/host/pci-dra7xx.c | 1 + drivers/pci/host/pci-exynos.c | 2 +- drivers/pci/host/pci-imx6.c | 2 +- drivers/pci/host/pci-keystone.c | 2 +- drivers/pci/host/pci-layerscape.c | 2 +- drivers/pci/host/pcie-designware.c | 242 +++++++++++++++---------------------- drivers/pci/host/pcie-designware.h | 10 +- drivers/pci/host/pcie-spear13xx.c | 2 +- 8 files changed, 109 insertions(+), 154 deletions(-) -------------------------------------------------- -------------------------------------------------- > -----Original Message----- > From: Wangzhou (B) > Sent: Thursday, June 11, 2015 6:44 AM > To: Gabriele Paoloni > Cc: Lorenzo Pieralisi; James Morse; Bjorn Helgaas; Jingoo Han; Pratyush > Anand; Arnd Bergmann; fabrice.gasnier@st.com; Liviu Dudau; linux- > pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > devicetree@vger.kernel.org; Yuanzhichang; Zhudacai; zhangjukuo; > qiuzhenfa; Liguozhu (Kenneth) > Subject: Re: [PATCH v2 2/4] PCI: designware: Add ARM64 support > > On 2015/6/10 21:35, Gabriele Paoloni wrote: > > Hi Zhou Wang and all > > > > I have worked on a patch that unify ARM and ARM64. As you can see I > have removed the parser and now I use > "of_pci_get_host_bridge_resources" in order to retrieve the resources > associated to each pci host bridge window. > > The resources now are not copied to the designware pcie_port pp, > instead they are passed by pointer. > > > > This patch is intended to replace entirely "[PATCH v2 2/4]"; so I > have also included all the changes about the other drivers > > > > Please find the patch inline below. > > > > Let me know if you think it is ok. > > > > Regards > > > > Gab > > > > ------------------------------------ > > ------------------------------------ > > > > This patch is a rework of > > "[PATCH v2 2/4] PCI: designware: Add ARM64 support" from Zhou Wang. > > > > The intention is to complete the unification between ARM and > > ARM64 now that the dependency on arch/arm/kernel/bios32.c is gone. > > > > I have also included the rework asked by James Morse: > > io_base declared as resource_size_t > > > > It compiles fine on ARCH arm and arm64. > > Hi Gabriele, > > I manually apply this patch on my series, as there are some format > errors > about this patch. And I think this patch is a experimental one, it > could not > be compiled successfully. > > > > > It needs to be tested. > > > > Signed-off-by: Gabriele Paoloni > > > > [...] > > > > -int dw_pcie_host_init(struct pcie_port *pp) > > +int __init dw_pcie_host_init(struct pcie_port *pp) > > { > > struct device_node *np = pp->dev->of_node; > > struct platform_device *pdev = to_platform_device(pp->dev); > > - struct of_pci_range range; > > - struct of_pci_range_parser parser; > > + struct pci_bus *bus; > > struct resource *cfg_res; > > + LIST_HEAD(res); > > u32 val, na, ns; > > const __be32 *addrp; > > int i, index, ret; > > + int rlen; > > + struct pci_host_bridge_window *win; > > This struct is not in latest kernel, I think you should use struct > resource_entry. > > Thanks, > Zhou > > > + const __be32 *parser_range_end = of_get_property(np, "ranges", > &rlen); > > + > > + if (parser_range_end == NULL) > > + return -ENOENT; > > + parser_range_end += rlen/sizeof(__be32); > > + > > > > /* Find the address cell size and the number of cells in order to > get > > * the untranslated address. > > @@ -375,78 +375,67 @@ int dw_pcie_host_init(struct pcie_port *pp) > > dev_err(pp->dev, "missing *config* reg space\n"); > > } > > > > - if (of_pci_range_parser_init(&parser, np)) { > > - dev_err(pp->dev, "missing ranges property\n"); > > - return -EINVAL; > > - } > > + ret = of_pci_get_host_bridge_resources(np, 0, 0xff, &res, &pp- > >io_base); > > + if (ret) > > + return ret; > > > > /* Get the I/O and memory ranges from DT */ > > - for_each_of_pci_range(&parser, &range) { > > - unsigned long restype = range.flags & IORESOURCE_TYPE_BITS; > > - > > - if (restype == IORESOURCE_IO) { > > - of_pci_range_to_resource(&range, np, &pp->io); > > - pp->io.name = "I/O"; > > - pp->io.start = max_t(resource_size_t, > > - PCIBIOS_MIN_IO, > > - range.pci_addr + global_io_offset); > > - pp->io.end = min_t(resource_size_t, > > - IO_SPACE_LIMIT, > > - range.pci_addr + range.size > > - + global_io_offset - 1); > > - pp->io_size = resource_size(&pp->io); > > - pp->io_bus_addr = range.pci_addr; > > - pp->io_base = range.cpu_addr; > > - > > - /* Find the untranslated IO space address */ > > - pp->io_mod_base = of_read_number(parser.range - > > - parser.np + na, ns); > > - } > > - if (restype == IORESOURCE_MEM) { > > - of_pci_range_to_resource(&range, np, &pp->mem); > > - pp->mem.name = "MEM"; > > - pp->mem_size = resource_size(&pp->mem); > > - pp->mem_bus_addr = range.pci_addr; > > - > > - /* Find the untranslated MEM space address */ > > - pp->mem_mod_base = of_read_number(parser.range - > > - parser.np + na, ns); > > - } > > - if (restype == 0) { > > - of_pci_range_to_resource(&range, np, &pp->cfg); > > - pp->cfg0_size = resource_size(&pp->cfg)/2; > > - pp->cfg1_size = resource_size(&pp->cfg)/2; > > - pp->cfg0_base = pp->cfg.start; > > - pp->cfg1_base = pp->cfg.start + pp->cfg0_size; > > + list_for_each_entry(win, &res, list) { > > + switch (resource_type(win->res)) { > > + case IORESOURCE_IO: > > + pp->io = win->res; > > + pp->io->name = "I/O"; > > + pp->io_size = resource_size(pp->io); > > + pp->io_bus_addr = pp->io->start - win->offset; > > + /* magic 5 below comes from magic na and ns in > > + * of_pci_range_parser_init() */ > > + pp->io_mod_base = of_read_number(parser_range_end - > > + of_n_addr_cells(np) - 5 + na, ns); > > + ret = pci_remap_iospace(pp->io, pp->io_base); > > + if (ret) { > > + dev_warn(pp->dev, "error %d: failed to map > resource %pR\n", > > + ret, pp->io); > > + continue; > > + } > > + break; > > + case IORESOURCE_MEM: > > + pp->mem = win->res; > > + pp->mem->name = "MEM"; > > + pp->mem_size = resource_size(pp->mem); > > + pp->mem_bus_addr = pp->mem->start - win->offset; > > + pp->mem_mod_base = of_read_number(parser_range_end - > > + of_n_addr_cells(np) - 5 + na, ns); > > + break; > > + case 0: > > + pp->cfg = win->res; > > + pp->cfg0_size = resource_size(pp->cfg)/2; > > + pp->cfg1_size = resource_size(pp->cfg)/2; > > + pp->cfg0_base = pp->cfg->start; > > + pp->cfg1_base = pp->cfg->start + pp->cfg0_size; > > > > /* Find the untranslated configuration space address > */ > > - pp->cfg0_mod_base = of_read_number(parser.range - > > - parser.np + na, ns); > > - pp->cfg1_mod_base = pp->cfg0_mod_base + > > - pp->cfg0_size; > > + pp->cfg0_mod_base = of_read_number(parser_range_end - > > + of_n_addr_cells(np) - 5 + na, ns); > > + pp->cfg1_mod_base = pp->cfg0_mod_base + pp->cfg0_size; > > + break; > > + case IORESOURCE_BUS: > > + pp->busn = win->res; > > + break; > > + default: > > + continue; > > } > > } > > > > - ret = of_pci_parse_bus_range(np, &pp->busn); > > - if (ret < 0) { > > - pp->busn.name = np->name; > > - pp->busn.start = 0; > > - pp->busn.end = 0xff; > > - pp->busn.flags = IORESOURCE_BUS; > > - dev_dbg(pp->dev, "failed to parse bus-range property: %d, > using default %pR\n", > > - ret, &pp->busn); > > - } > > - > > if (!pp->dbi_base) { > > - pp->dbi_base = devm_ioremap(pp->dev, pp->cfg.start, > > - resource_size(&pp->cfg)); > > + pp->dbi_base = devm_ioremap(pp->dev, pp->cfg->start, > > + resource_size(pp->cfg)); > > if (!pp->dbi_base) { > > dev_err(pp->dev, "error with ioremap\n"); > > return -ENOMEM; > > } > > } > > > > - pp->mem_base = pp->mem.start; > > + pp->mem_base = pp->mem->start; > > > > if (!pp->va_cfg0_base) { > > pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base, @@ > -493,24 +482,47 @@ int dw_pcie_host_init(struct pcie_port *pp) > > if (pp->ops->host_init) > > pp->ops->host_init(pp); > > > > - dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); > > + if (dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0) > > + != PCIBIOS_SUCCESSFUL) > > + return -EINVAL; > > > > /* program correct class for RC */ > > - dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, > PCI_CLASS_BRIDGE_PCI); > > + if (dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, > PCI_CLASS_BRIDGE_PCI) > > + != PCIBIOS_SUCCESSFUL) > > + return -EINVAL; > > + > > + if (dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, > &val) > > + != PCIBIOS_SUCCESSFUL) > > + return -EINVAL; > > > > - dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val); > > val |= PORT_LOGIC_SPEED_CHANGE; > > - dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); > > > > -#ifdef CONFIG_PCI_MSI > > - dw_pcie_msi_chip.dev = pp->dev; > > - dw_pci.msi_ctrl = &dw_pcie_msi_chip; > > + if (dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val) > > + != PCIBIOS_SUCCESSFUL) > > + return -EINVAL; > > + > > + bus = pci_create_root_bus(pp->dev, pp->root_bus_nr, &dw_pcie_ops, > > + pp, &res); > > + if (!bus) > > + return -ENOMEM; > > + > > +#ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN > > + bus->msi = container_of(&pp->irq_domain, struct msi_controller, > > +domain); #else > > + bus->msi = &dw_pcie_msi_chip; > > #endif > > > > - dw_pci.nr_controllers = 1; > > - dw_pci.private_data = (void **)&pp; > > + pci_scan_child_bus(bus); > > + if (pp->ops->scan_bus) > > + pp->ops->scan_bus(pp); > > > > - pci_common_init_dev(pp->dev, &dw_pci); > > +#ifdef CONFIG_ARM > > + /* support old dtbs that incorrectly describe IRQs */ > > + pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci); > #endif > > + > > + pci_assign_unassigned_bus_resources(bus); > > + pci_bus_add_devices(bus); > > > > return 0; > > } > > @@ -653,7 +665,7 @@ static int dw_pcie_valid_config(struct pcie_port > *pp, static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int > where, > > int size, u32 *val) > > { > > - struct pcie_port *pp = sys_to_pcie(bus->sysdata); > > + struct pcie_port *pp = bus->sysdata; > > int ret; > > > > if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) { @@ - > 677,7 +689,7 @@ static int dw_pcie_rd_conf(struct pci_bus *bus, u32 > devfn, int where, static int dw_pcie_wr_conf(struct pci_bus *bus, u32 > devfn, > > int where, int size, u32 val) > > { > > - struct pcie_port *pp = sys_to_pcie(bus->sysdata); > > + struct pcie_port *pp = bus->sysdata; > > int ret; > > > > if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) @@ - > 701,64 +713,6 @@ static struct pci_ops dw_pcie_ops = { > > .write = dw_pcie_wr_conf, > > }; > > > > -static int dw_pcie_setup(int nr, struct pci_sys_data *sys) -{ > > - struct pcie_port *pp; > > - > > - pp = sys_to_pcie(sys); > > - > > - if (global_io_offset < SZ_1M && pp->io_size > 0) { > > - sys->io_offset = global_io_offset - pp->io_bus_addr; > > - pci_ioremap_io(global_io_offset, pp->io_base); > > - global_io_offset += SZ_64K; > > - pci_add_resource_offset(&sys->resources, &pp->io, > > - sys->io_offset); > > - } > > - > > - sys->mem_offset = pp->mem.start - pp->mem_bus_addr; > > - pci_add_resource_offset(&sys->resources, &pp->mem, sys- > >mem_offset); > > - pci_add_resource(&sys->resources, &pp->busn); > > - > > - return 1; > > -} > > - > > -static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data > *sys) -{ > > - struct pci_bus *bus; > > - struct pcie_port *pp = sys_to_pcie(sys); > > - > > - pp->root_bus_nr = sys->busnr; > > - bus = pci_create_root_bus(pp->dev, sys->busnr, > > - &dw_pcie_ops, sys, &sys->resources); > > - if (!bus) > > - return NULL; > > - > > - pci_scan_child_bus(bus); > > - > > - if (bus && pp->ops->scan_bus) > > - pp->ops->scan_bus(pp); > > - > > - return bus; > > -} > > - > > -static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 > pin) -{ > > - struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata); > > - int irq; > > - > > - irq = of_irq_parse_and_map_pci(dev, slot, pin); > > - if (!irq) > > - irq = pp->irq; > > - > > - return irq; > > -} > > - > > -static struct hw_pci dw_pci = { > > - .setup = dw_pcie_setup, > > - .scan = dw_pcie_scan_bus, > > - .map_irq = dw_pcie_map_irq, > > -}; > > - > > void dw_pcie_setup_rc(struct pcie_port *pp) { > > u32 val; > > diff --git a/drivers/pci/host/pcie-designware.h > b/drivers/pci/host/pcie-designware.h > > index d0bbd27..ab78710 100644 > > --- a/drivers/pci/host/pcie-designware.h > > +++ b/drivers/pci/host/pcie-designware.h > > @@ -34,7 +34,7 @@ struct pcie_port { > > u64 cfg1_mod_base; > > void __iomem *va_cfg1_base; > > u32 cfg1_size; > > - u64 io_base; > > + resource_size_t io_base; > > u64 io_mod_base; > > phys_addr_t io_bus_addr; > > u32 io_size; > > @@ -42,10 +42,10 @@ struct pcie_port { > > u64 mem_mod_base; > > phys_addr_t mem_bus_addr; > > u32 mem_size; > > - struct resource cfg; > > - struct resource io; > > - struct resource mem; > > - struct resource busn; > > + struct resource *cfg; > > + struct resource *io; > > + struct resource *mem; > > + struct resource *busn; > > int irq; > > u32 lanes; > > struct pcie_host_ops *ops; > > diff --git a/drivers/pci/host/pcie-spear13xx.c > b/drivers/pci/host/pcie-spear13xx.c > > index 020d788..e78ddf8 100644 > > --- a/drivers/pci/host/pcie-spear13xx.c > > +++ b/drivers/pci/host/pcie-spear13xx.c > > @@ -287,7 +287,7 @@ static int spear13xx_add_pcie_port(struct > pcie_port *pp, > > return ret; > > } > > > > - pp->root_bus_nr = -1; > > + pp->root_bus_nr = 0; > > pp->ops = &spear13xx_pcie_host_ops; > > > > ret = dw_pcie_host_init(pp); > > ------------------------------------ > > ------------------------------------ > > > > > > > > > >> -----Original Message----- > >> From: Lorenzo Pieralisi [mailto:lorenzo.pieralisi@arm.com] > >> Sent: Tuesday, June 09, 2015 12:15 PM > >> To: Wangzhou (B) > >> Cc: James Morse; Bjorn Helgaas; Jingoo Han; Pratyush Anand; Arnd > >> Bergmann; fabrice.gasnier@st.com; Liviu Dudau; linux- > >> pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > >> devicetree@vger.kernel.org; Gabriele Paoloni; Yuanzhichang; Zhudacai; > >> zhangjukuo; qiuzhenfa; Liguozhu (Kenneth) > >> Subject: Re: [PATCH v2 2/4] PCI: designware: Add ARM64 support > >> > >> On Fri, Jun 05, 2015 at 09:11:30AM +0100, Zhou Wang wrote: > >> > >> [...] > >> > >>>>> -int dw_pcie_host_init(struct pcie_port *pp) > >>>>> +int __init dw_pcie_host_init(struct pcie_port *pp) > >>>>> { > >>>>> struct device_node *np = pp->dev->of_node; > >>>>> struct platform_device *pdev = to_platform_device(pp->dev); > >>>>> struct of_pci_range range; > >>>>> struct of_pci_range_parser parser; > >>>>> + struct pci_bus *bus; > >>>>> struct resource *cfg_res; > >>>>> + LIST_HEAD(res); > >>>>> u32 val, na, ns; > >>>>> const __be32 *addrp; > >>>>> int i, index, ret; > >>>>> @@ -502,15 +498,49 @@ int dw_pcie_host_init(struct pcie_port *pp) > >>>>> val |= PORT_LOGIC_SPEED_CHANGE; > >>>>> dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, > >> val); > >>>>> > >>>>> -#ifdef CONFIG_PCI_MSI > >>>>> - dw_pcie_msi_chip.dev = pp->dev; > >>>>> - dw_pci.msi_ctrl = &dw_pcie_msi_chip; > >>>>> +#ifdef CONFIG_ARM > >>>>> + /* > >>>>> + * FIXME: we should really be able to use > >>>>> + * of_pci_get_host_bridge_resources on arm32 as well, > >>>>> + * but the conversion needs some more testing > >>>>> + */ > >>>>> + if (global_io_offset < SZ_1M && pp->io_size > 0) { > >>>>> + pci_ioremap_io(global_io_offset, pp->io_base); > >>>>> + global_io_offset += SZ_64K; > >>>>> + pci_add_resource_offset(&res, &pp->io, > >>>>> + global_io_offset - pp->io_bus_addr); > >>>>> + } > >>>>> + pci_add_resource_offset(&res, &pp->mem, > >>>>> + pp->mem.start - pp->mem_bus_addr); > >>>>> + pci_add_resource(&res, &pp->busn); > >>>> > >>>> I don't think this #ifdef is necessary. In the spirit of 'the > >>>> conversion needs some more testing', I removed it leaving just the > >> below arm64 code. > >>>> > >>>> This worked on my Freescale i.MX6 Quad SABRE Lite Board, I went as > >>>> far as scanning for wireless access points. > >>>> > >>> > >>> I think it depends on which kind of PCIe device you use, if we use > a > >>> PCIe device with a I/O Bar, it may not work well without above code. > >>> But so far, I have not met a PCIe device which must work with a I/O > >> Bar. > >> > >> There are two problems here: > >> > >> 1) the io_base address you get from of_pci_get_host_bridge_resources > >> must be mapped using pci_remap_iospace. You are not doing this, > so > >> even if you had a PCIe card with I/O bar it would not work on > arm64 > >> as the code stands. Remember that I/O space on arm/arm64 works as > a > >> memory access with offset from PCI_IOBASE and that's the value > you > >> get > >> in the I/O resource. See: > >> > >> drivers/pci/host/pci-host-generic.c > >> drivers/pci/host/pci-versatile.c > >> drivers/pci/host/pci-xgene.c > >> > >> 2) (1) above would sort out I/O space access for both arm and arm64 > so, > >> as James said, the #ifdef is useless. > >> > >> I hope this makes things clearer. > >> > >> Thanks, > >> Lorenzo > >> > >>> > >>>>> +#else > >>>>> + ret = of_pci_get_host_bridge_resources(np, 0, 0xff, &res, > >>>>> +&pp->io_base); > >>>> > >>>> of_pci_get_host_bridge_resources expects &pp->io_base to be a > >>>> resource_size_t*, but &io_base is u64*. This generates a warning > on > >>>> arm with the above change. Changing the the type in > >>>> drivers/pci/host/pcie-designware.h fixes this. > >>>> > >>>> > >>>> Thanks, > >>>> > >>>> James > >>>> > >>> > >>> OK, will modify this in next version. > >>> > >>> Best Regards and thanks again for your test, Zhou > >>> > >>>>> + if (ret) > >>>>> + return ret; > >>>>> +#endif > >>>>> + > >>>>> + bus = pci_create_root_bus(pp->dev, pp->root_bus_nr, > >> &dw_pcie_ops, > >>>>> + pp, &res); > >>>>> + if (!bus) > >>>>> + return -ENOMEM; > >>>>> + > >>>>> +#ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN > >>>>> + bus->msi = container_of(&pp->irq_domain, struct > >> msi_controller, > >>>>> +domain); #else > >>>>> + bus->msi = &dw_pcie_msi_chip; > >>>>> #endif > >>>>> > >>>>> - dw_pci.nr_controllers = 1; > >>>>> - dw_pci.private_data = (void **)&pp; > >>>>> + pci_scan_child_bus(bus); > >>>>> + if (pp->ops->scan_bus) > >>>>> + pp->ops->scan_bus(pp); > >>>>> > >>>>> - pci_common_init_dev(pp->dev, &dw_pci); > >>>>> +#ifdef CONFIG_ARM > >>>>> + /* support old dtbs that incorrectly describe IRQs */ > >>>>> + pci_fixup_irqs(pci_common_swizzle, > >> of_irq_parse_and_map_pci); > >>>>> +#endif > >>>>> + > >>>>> + pci_assign_unassigned_bus_resources(bus); > >>>>> + pci_bus_add_devices(bus); > >>>>> > >>>>> return 0; > >>>>> } > >>>>> @@ -653,7 +683,7 @@ static int dw_pcie_valid_config(struct > >>>>> pcie_port *pp, static int dw_pcie_rd_conf(struct pci_bus *bus, > >> u32 devfn, int where, > >>>>> int size, u32 *val) > >>>>> { > >>>>> - struct pcie_port *pp = sys_to_pcie(bus->sysdata); > >>>>> + struct pcie_port *pp = bus->sysdata; > >>>>> int ret; > >>>>> > >>>>> if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) > >> { @@ > >>>>> -677,7 +707,7 @@ static int dw_pcie_rd_conf(struct pci_bus *bus, > >>>>> u32 devfn, int where, static int dw_pcie_wr_conf(struct pci_bus > >> *bus, u32 devfn, > >>>>> int where, int size, u32 val) > >>>>> { > >>>>> - struct pcie_port *pp = sys_to_pcie(bus->sysdata); > >>>>> + struct pcie_port *pp = bus->sysdata; > >>>>> int ret; > >>>>> > >>>>> if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) @@ > >>>>> -701,64 +731,6 @@ static struct pci_ops dw_pcie_ops = { > >>>>> .write = dw_pcie_wr_conf, > >>>>> }; > >>>>> > >>>>> -static int dw_pcie_setup(int nr, struct pci_sys_data *sys) -{ > >>>>> - struct pcie_port *pp; > >>>>> - > >>>>> - pp = sys_to_pcie(sys); > >>>>> - > >>>>> - if (global_io_offset < SZ_1M && pp->io_size > 0) { > >>>>> - sys->io_offset = global_io_offset - pp->io_bus_addr; > >>>>> - pci_ioremap_io(global_io_offset, pp->io_base); > >>>>> - global_io_offset += SZ_64K; > >>>>> - pci_add_resource_offset(&sys->resources, &pp->io, > >>>>> - sys->io_offset); > >>>>> - } > >>>>> - > >>>>> - sys->mem_offset = pp->mem.start - pp->mem_bus_addr; > >>>>> - pci_add_resource_offset(&sys->resources, &pp->mem, sys- > >>> mem_offset); > >>>>> - pci_add_resource(&sys->resources, &pp->busn); > >>>>> - > >>>>> - return 1; > >>>>> -} > >>>>> - > >>>>> -static struct pci_bus *dw_pcie_scan_bus(int nr, struct > >>>>> pci_sys_data *sys) -{ > >>>>> - struct pci_bus *bus; > >>>>> - struct pcie_port *pp = sys_to_pcie(sys); > >>>>> - > >>>>> - pp->root_bus_nr = sys->busnr; > >>>>> - bus = pci_create_root_bus(pp->dev, sys->busnr, > >>>>> - &dw_pcie_ops, sys, &sys->resources); > >>>>> - if (!bus) > >>>>> - return NULL; > >>>>> - > >>>>> - pci_scan_child_bus(bus); > >>>>> - > >>>>> - if (bus && pp->ops->scan_bus) > >>>>> - pp->ops->scan_bus(pp); > >>>>> - > >>>>> - return bus; > >>>>> -} > >>>>> - > >>>>> -static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, > u8 > >>>>> pin) -{ > >>>>> - struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata); > >>>>> - int irq; > >>>>> - > >>>>> - irq = of_irq_parse_and_map_pci(dev, slot, pin); > >>>>> - if (!irq) > >>>>> - irq = pp->irq; > >>>>> - > >>>>> - return irq; > >>>>> -} > >>>>> - > >>>>> -static struct hw_pci dw_pci = { > >>>>> - .setup = dw_pcie_setup, > >>>>> - .scan = dw_pcie_scan_bus, > >>>>> - .map_irq = dw_pcie_map_irq, > >>>>> -}; > >>>>> - > >>>>> void dw_pcie_setup_rc(struct pcie_port *pp) { > >>>>> u32 val; > >>>> > >>>> > >>>> . > >>>> > >>> > >>> > >>> -- > >>> To unsubscribe from this list: send the line "unsubscribe linux- > pci" > >>> in the body of a message to majordomo@vger.kernel.org More > majordomo > >>> info at http://vger.kernel.org/majordomo-info.html > >>> > > > > . > > > diff --git a/drivers/pci/host/pci-dra7xx.c b/drivers/pci/host/pci-dra7xx.c index 2d57e19..5c8b6ab 100644 --- a/drivers/pci/host/pci-dra7xx.c +++ b/drivers/pci/host/pci-dra7xx.c @@ -280,6 +280,7 @@ static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx, pp = &dra7xx->pp; pp->dev = dev; + pp->root_bus_nr = 0; pp->ops = &dra7xx_pcie_host_ops; pp->irq = platform_get_irq(pdev, 1); diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c index c139237..4b6db6c 100644 --- a/drivers/pci/host/pci-exynos.c +++ b/drivers/pci/host/pci-exynos.c @@ -534,7 +534,7 @@ static int __init exynos_add_pcie_port(struct pcie_port *pp, } } - pp->root_bus_nr = -1; + pp->root_bus_nr = 0; pp->ops = &exynos_pcie_host_ops; ret = dw_pcie_host_init(pp); diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c index fdb9536..c4a80c5 100644 --- a/drivers/pci/host/pci-imx6.c +++ b/drivers/pci/host/pci-imx6.c @@ -541,7 +541,7 @@ static int __init imx6_add_pcie_port(struct pcie_port *pp, } } - pp->root_bus_nr = -1; + pp->root_bus_nr = 0; pp->ops = &imx6_pcie_host_ops; ret = dw_pcie_host_init(pp); diff --git a/drivers/pci/host/pci-keystone.c b/drivers/pci/host/pci-keystone.c index 75333b0..df91f5e 100644 --- a/drivers/pci/host/pci-keystone.c +++ b/drivers/pci/host/pci-keystone.c @@ -312,7 +312,7 @@ static int __init ks_add_pcie_port(struct keystone_pcie *ks_pcie, return ret; } - pp->root_bus_nr = -1; + pp->root_bus_nr = 0; pp->ops = &keystone_pcie_host_ops; ret = ks_dw_pcie_host_init(ks_pcie, ks_pcie->msi_intc_np); if (ret) { diff --git a/drivers/pci/host/pci-layerscape.c b/drivers/pci/host/pci-layerscape.c index 4a6e62f..5c7a9c4 100644 --- a/drivers/pci/host/pci-layerscape.c +++ b/drivers/pci/host/pci-layerscape.c @@ -101,7 +101,7 @@ static int ls_add_pcie_port(struct ls_pcie *pcie) pp = &pcie->pp; pp->dev = pcie->dev; pp->dbi_base = pcie->dbi; - pp->root_bus_nr = -1; + pp->root_bus_nr = 0; pp->ops = &ls_pcie_host_ops; ret = dw_pcie_host_init(pp); diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index 2e9f84f..844febee 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -11,6 +11,7 @@ * published by the Free Software Foundation. */ +#include #include #include #include @@ -67,16 +68,7 @@ #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) #define PCIE_ATU_UPPER_TARGET 0x91C -static struct hw_pci dw_pci; - -static unsigned long global_io_offset; - -static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys) -{ - BUG_ON(!sys->private_data); - - return sys->private_data; -} +static struct pci_ops dw_pcie_ops; int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val) { @@ -238,7 +230,7 @@ static void dw_pcie_msi_set_irq(struct pcie_port *pp, int irq) static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos) { int irq, pos0, i; - struct pcie_port *pp = sys_to_pcie(desc->dev->bus->sysdata); + struct pcie_port *pp = desc->dev->bus->sysdata; pos0 = bitmap_find_free_region(pp->msi_irq_in_use, MAX_MSI_IRQS, order_base_2(no_irqs)); @@ -281,7 +273,7 @@ static int dw_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev, { int irq, pos; struct msi_msg msg; - struct pcie_port *pp = sys_to_pcie(pdev->bus->sysdata); + struct pcie_port *pp = pdev->bus->sysdata; if (desc->msi_attrib.is_msix) return -EINVAL; @@ -310,7 +302,7 @@ static void dw_msi_teardown_irq(struct msi_controller *chip, unsigned int irq) { struct irq_data *data = irq_get_irq_data(irq); struct msi_desc *msi = irq_data_get_msi(data); - struct pcie_port *pp = sys_to_pcie(msi->dev->bus->sysdata); + struct pcie_port *pp = msi->dev->bus->sysdata; clear_irq_range(pp, irq, 1, data->hwirq); } @@ -342,16 +334,24 @@ static const struct irq_domain_ops msi_domain_ops = { .map = dw_pcie_msi_map, }; -int dw_pcie_host_init(struct pcie_port *pp) +int __init dw_pcie_host_init(struct pcie_port *pp) { struct device_node *np = pp->dev->of_node; struct platform_device *pdev = to_platform_device(pp->dev); - struct of_pci_range range; - struct of_pci_range_parser parser; + struct pci_bus *bus; struct resource *cfg_res; + LIST_HEAD(res); u32 val, na, ns; const __be32 *addrp; int i, index, ret; + int rlen; + struct resource_entry *win; + const __be32 *parser_range_end = of_get_property(np, "ranges", &rlen); + + if (parser_range_end == NULL) + return -ENOENT; + parser_range_end += rlen/sizeof(__be32); + /* Find the address cell size and the number of cells in order to get * the untranslated address. @@ -375,78 +375,67 @@ int dw_pcie_host_init(struct pcie_port *pp) dev_err(pp->dev, "missing *config* reg space\n"); } - if (of_pci_range_parser_init(&parser, np)) { - dev_err(pp->dev, "missing ranges property\n"); - return -EINVAL; - } + ret = of_pci_get_host_bridge_resources(np, 0, 0xff, &res, &pp->io_base); + if (ret) + return ret; /* Get the I/O and memory ranges from DT */ - for_each_of_pci_range(&parser, &range) { - unsigned long restype = range.flags & IORESOURCE_TYPE_BITS; - - if (restype == IORESOURCE_IO) { - of_pci_range_to_resource(&range, np, &pp->io); - pp->io.name = "I/O"; - pp->io.start = max_t(resource_size_t, - PCIBIOS_MIN_IO, - range.pci_addr + global_io_offset); - pp->io.end = min_t(resource_size_t, - IO_SPACE_LIMIT, - range.pci_addr + range.size - + global_io_offset - 1); - pp->io_size = resource_size(&pp->io); - pp->io_bus_addr = range.pci_addr; - pp->io_base = range.cpu_addr; - - /* Find the untranslated IO space address */ - pp->io_mod_base = of_read_number(parser.range - - parser.np + na, ns); - } - if (restype == IORESOURCE_MEM) { - of_pci_range_to_resource(&range, np, &pp->mem); - pp->mem.name = "MEM"; - pp->mem_size = resource_size(&pp->mem); - pp->mem_bus_addr = range.pci_addr; - - /* Find the untranslated MEM space address */ - pp->mem_mod_base = of_read_number(parser.range - - parser.np + na, ns); - } - if (restype == 0) { - of_pci_range_to_resource(&range, np, &pp->cfg); - pp->cfg0_size = resource_size(&pp->cfg)/2; - pp->cfg1_size = resource_size(&pp->cfg)/2; - pp->cfg0_base = pp->cfg.start; - pp->cfg1_base = pp->cfg.start + pp->cfg0_size; + resource_list_for_each_entry(win, &res) { + switch (resource_type(win->res)) { + case IORESOURCE_IO: + pp->io = win->res; + pp->io->name = "I/O"; + pp->io_size = resource_size(pp->io); + pp->io_bus_addr = pp->io->start - win->offset; + /* magic 5 below comes from magic na and ns in + * of_pci_range_parser_init() */ + pp->io_mod_base = of_read_number(parser_range_end - + of_n_addr_cells(np) - 5 + na, ns); + ret = pci_remap_iospace(pp->io, pp->io_base); + if (ret) { + dev_warn(pp->dev, "error %d: failed to map resource %pR\n", + ret, pp->io); + continue; + } + break; + case IORESOURCE_MEM: + pp->mem = win->res; + pp->mem->name = "MEM"; + pp->mem_size = resource_size(pp->mem); + pp->mem_bus_addr = pp->mem->start - win->offset; + pp->mem_mod_base = of_read_number(parser_range_end - + of_n_addr_cells(np) - 5 + na, ns); + break; + case 0: + pp->cfg = win->res; + pp->cfg0_size = resource_size(pp->cfg)/2; + pp->cfg1_size = resource_size(pp->cfg)/2; + pp->cfg0_base = pp->cfg->start; + pp->cfg1_base = pp->cfg->start + pp->cfg0_size; /* Find the untranslated configuration space address */ - pp->cfg0_mod_base = of_read_number(parser.range - - parser.np + na, ns); - pp->cfg1_mod_base = pp->cfg0_mod_base + - pp->cfg0_size; + pp->cfg0_mod_base = of_read_number(parser_range_end - + of_n_addr_cells(np) - 5 + na, ns); + pp->cfg1_mod_base = pp->cfg0_mod_base + pp->cfg0_size; + break; + case IORESOURCE_BUS: + pp->busn = win->res; + break; + default: + continue; } } - ret = of_pci_parse_bus_range(np, &pp->busn); - if (ret < 0) { - pp->busn.name = np->name; - pp->busn.start = 0; - pp->busn.end = 0xff; - pp->busn.flags = IORESOURCE_BUS; - dev_dbg(pp->dev, "failed to parse bus-range property: %d, using default %pR\n", - ret, &pp->busn); - } - if (!pp->dbi_base) { - pp->dbi_base = devm_ioremap(pp->dev, pp->cfg.start, - resource_size(&pp->cfg)); + pp->dbi_base = devm_ioremap(pp->dev, pp->cfg->start, + resource_size(pp->cfg)); if (!pp->dbi_base) { dev_err(pp->dev, "error with ioremap\n"); return -ENOMEM; } } - pp->mem_base = pp->mem.start; + pp->mem_base = pp->mem->start; if (!pp->va_cfg0_base) { pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base, @@ -493,24 +482,47 @@ int dw_pcie_host_init(struct pcie_port *pp) if (pp->ops->host_init) pp->ops->host_init(pp); - dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); + if (dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0) + != PCIBIOS_SUCCESSFUL) + return -EINVAL; /* program correct class for RC */ - dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); + if (dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI) + != PCIBIOS_SUCCESSFUL) + return -EINVAL; + + if (dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val) + != PCIBIOS_SUCCESSFUL) + return -EINVAL; - dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val); val |= PORT_LOGIC_SPEED_CHANGE; - dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); -#ifdef CONFIG_PCI_MSI - dw_pcie_msi_chip.dev = pp->dev; - dw_pci.msi_ctrl = &dw_pcie_msi_chip; + if (dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val) + != PCIBIOS_SUCCESSFUL) + return -EINVAL; + + bus = pci_create_root_bus(pp->dev, pp->root_bus_nr, &dw_pcie_ops, + pp, &res); + if (!bus) + return -ENOMEM; + +#ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN + bus->msi = container_of(&pp->irq_domain, struct msi_controller, domain); +#else + bus->msi = &dw_pcie_msi_chip; #endif - dw_pci.nr_controllers = 1; - dw_pci.private_data = (void **)&pp; + pci_scan_child_bus(bus); + if (pp->ops->scan_bus) + pp->ops->scan_bus(pp); - pci_common_init_dev(pp->dev, &dw_pci); +#ifdef CONFIG_ARM + /* support old dtbs that incorrectly describe IRQs */ + pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci); +#endif + + pci_assign_unassigned_bus_resources(bus); + pci_bus_add_devices(bus); return 0; } @@ -653,7 +665,7 @@ static int dw_pcie_valid_config(struct pcie_port *pp, static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 *val) { - struct pcie_port *pp = sys_to_pcie(bus->sysdata); + struct pcie_port *pp = bus->sysdata; int ret; if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) { @@ -677,7 +689,7 @@ static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 val) { - struct pcie_port *pp = sys_to_pcie(bus->sysdata); + struct pcie_port *pp = bus->sysdata; int ret; if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) @@ -701,64 +713,6 @@ static struct pci_ops dw_pcie_ops = { .write = dw_pcie_wr_conf, }; -static int dw_pcie_setup(int nr, struct pci_sys_data *sys) -{ - struct pcie_port *pp; - - pp = sys_to_pcie(sys); - - if (global_io_offset < SZ_1M && pp->io_size > 0) { - sys->io_offset = global_io_offset - pp->io_bus_addr; - pci_ioremap_io(global_io_offset, pp->io_base); - global_io_offset += SZ_64K; - pci_add_resource_offset(&sys->resources, &pp->io, - sys->io_offset); - } - - sys->mem_offset = pp->mem.start - pp->mem_bus_addr; - pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset); - pci_add_resource(&sys->resources, &pp->busn); - - return 1; -} - -static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys) -{ - struct pci_bus *bus; - struct pcie_port *pp = sys_to_pcie(sys); - - pp->root_bus_nr = sys->busnr; - bus = pci_create_root_bus(pp->dev, sys->busnr, - &dw_pcie_ops, sys, &sys->resources); - if (!bus) - return NULL; - - pci_scan_child_bus(bus); - - if (bus && pp->ops->scan_bus) - pp->ops->scan_bus(pp); - - return bus; -} - -static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata); - int irq; - - irq = of_irq_parse_and_map_pci(dev, slot, pin); - if (!irq) - irq = pp->irq; - - return irq; -} - -static struct hw_pci dw_pci = { - .setup = dw_pcie_setup, - .scan = dw_pcie_scan_bus, - .map_irq = dw_pcie_map_irq, -}; - void dw_pcie_setup_rc(struct pcie_port *pp) { u32 val; diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h index d0bbd27..ab78710 100644 --- a/drivers/pci/host/pcie-designware.h +++ b/drivers/pci/host/pcie-designware.h @@ -34,7 +34,7 @@ struct pcie_port { u64 cfg1_mod_base; void __iomem *va_cfg1_base; u32 cfg1_size; - u64 io_base; + resource_size_t io_base; u64 io_mod_base; phys_addr_t io_bus_addr; u32 io_size; @@ -42,10 +42,10 @@ struct pcie_port { u64 mem_mod_base; phys_addr_t mem_bus_addr; u32 mem_size; - struct resource cfg; - struct resource io; - struct resource mem; - struct resource busn; + struct resource *cfg; + struct resource *io; + struct resource *mem; + struct resource *busn; int irq; u32 lanes; struct pcie_host_ops *ops; diff --git a/drivers/pci/host/pcie-spear13xx.c b/drivers/pci/host/pcie-spear13xx.c index 020d788..e78ddf8 100644 --- a/drivers/pci/host/pcie-spear13xx.c +++ b/drivers/pci/host/pcie-spear13xx.c @@ -287,7 +287,7 @@ static int spear13xx_add_pcie_port(struct pcie_port *pp, return ret; } - pp->root_bus_nr = -1; + pp->root_bus_nr = 0; pp->ops = &spear13xx_pcie_host_ops; ret = dw_pcie_host_init(pp);