From patchwork Fri Dec 28 11:32:54 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guennadi Liakhovetski X-Patchwork-Id: 1915041 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id BF85A40061 for ; Fri, 28 Dec 2012 11:36:05 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1ToYBm-00044S-Jw; Fri, 28 Dec 2012 11:33:22 +0000 Received: from moutng.kundenserver.de ([212.227.126.186]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1ToYBh-00043K-JF for linux-arm-kernel@lists.infradead.org; Fri, 28 Dec 2012 11:33:20 +0000 Received: from axis700.grange (dslb-178-006-245-116.pools.arcor-ip.net [178.6.245.116]) by mrelayeu.kundenserver.de (node=mreu2) with ESMTP (Nemesis) id 0Lgt3C-1TJ7RI3Bm2-00ncoT; Fri, 28 Dec 2012 12:32:55 +0100 Received: by axis700.grange (Postfix, from userid 1000) id 3891E40B99; Fri, 28 Dec 2012 12:32:54 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by axis700.grange (Postfix) with ESMTP id 2B6EB40B98; Fri, 28 Dec 2012 12:32:54 +0100 (CET) Date: Fri, 28 Dec 2012 12:32:54 +0100 (CET) From: Guennadi Liakhovetski X-X-Sender: lyakh@axis700.grange To: Santosh Shilimkar Subject: [PATCH v2] ARM: sh7372: fix cache clean / invalidate order In-Reply-To: <50C9E8BD.1020501@ti.com> Message-ID: References: <20120919134658.GA2111@linaro.org> <20120920102514.GD4588@e102568-lin.cambridge.arm.com> <20120920110439.GB2117@linaro.org> <20121211163313.GG16759@mudshark.cambridge.arm.com> <20121211163843.GH16759@mudshark.cambridge.arm.com> <50C7C16B.7050106@codeaurora.org> <20121212103338.GB23022@e102568-lin.cambridge.arm.com> <20121212133650.GJ6195@mudshark.cambridge.arm.com> <20121213105109.GB26540@mudshark.cambridge.arm.com> <50C9E8BD.1020501@ti.com> MIME-Version: 1.0 X-Provags-ID: V02:K0:CTw8ZZFP3e7ZMZilcL2ae3FsLg+sY++j9WQ+QJLQiPl t6jOvZ1ZV1DfGaIQbHz5DyvmozwFWfaXe9MZfAQcxsa2Rrd9Mg LOmkNAcFqXSo9xamvCmlavOmUOk1gZxdhrIAHmMoAy0Uz5Imx4 hQyHHzCuqc5T54eKxPPS+sNiaEr4eb8uSmmM2ToVbICwmok/U5 aYe7ppfNa7GDIAgcZcoqNzjOj/CxLx+Y89cT/MER07Yg4h/Tuh 9BSihOmruN53RJEBcRjLsxD9XJKQvzjCn5y8iMXjXDSxT3Th3J yawYwPGiEVYAUCEDk/TAm8nYpvWhIgIhKT7hx+ynVs6sZMcauH ZHXdw11FrDFZA9Jl1CApqZWBoJ6f/OcyrtHLJ0+7zT/fr81jTd DXve6gDXj617g== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121228_063317_874533_1B42D130 X-CRM114-Status: UNSURE ( 8.68 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (g.liakhovetski[at]gmx.de) -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [212.227.126.186 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Nicolas Pitre , Dave Martin , Lorenzo Pieralisi , Russell King , "linux-sh@vger.kernel.org" , Catalin Marinas , Daniel Lezcano , Will Deacon , Amit Kucheria , Simon Horman , Colin Cross , "linux-omap@vger.kernel.org" , Wenzeng Chen , Stephen Boyd , "linux-arm-kernel@lists.infradead.org" , Magnus Damm X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org According to the Cortex A8 TRM the L2 cache should be first cleaned and then disabled. Fix the swapped order on sh7372. Signed-off-by: Guennadi Liakhovetski Reviewed-by: Santosh Shilimkar --- v2: addressed improvement suggestions by Santosh, thanks diff --git a/arch/arm/mach-shmobile/sleep-sh7372.S b/arch/arm/mach-shmobile/sleep-sh7372.S index 1d56467..a9df53b 100644 --- a/arch/arm/mach-shmobile/sleep-sh7372.S +++ b/arch/arm/mach-shmobile/sleep-sh7372.S @@ -59,17 +59,19 @@ sh7372_do_idle_sysc: mcr p15, 0, r0, c1, c0, 0 isb + /* + * Clean and invalidate data cache again. + */ + ldr r1, kernel_flush + blx r1 + /* disable L2 cache in the aux control register */ mrc p15, 0, r10, c1, c0, 1 bic r10, r10, #2 mcr p15, 0, r10, c1, c0, 1 + isb /* - * Invalidate data cache again. - */ - ldr r1, kernel_flush - blx r1 - /* * The kernel doesn't interwork: v7_flush_dcache_all in particluar will * always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled. * This sequence switches back to ARM. Note that .align may insert a