From patchwork Wed Apr 3 09:19:03 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guennadi Liakhovetski X-Patchwork-Id: 2385811 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id B81DCDFB79 for ; Wed, 3 Apr 2013 09:22:19 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UNJqb-0005al-BW; Wed, 03 Apr 2013 09:19:13 +0000 Received: from moutng.kundenserver.de ([212.227.17.9]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UNJqX-0005YN-15 for linux-arm-kernel@lists.infradead.org; Wed, 03 Apr 2013 09:19:10 +0000 Received: from axis700.grange (dslb-094-221-105-117.pools.arcor-ip.net [94.221.105.117]) by mrelayeu.kundenserver.de (node=mrbap1) with ESMTP (Nemesis) id 0M6wYn-1Ub7L83IF3-00wbKh; Wed, 03 Apr 2013 11:19:04 +0200 Received: by axis700.grange (Postfix, from userid 1000) id 68A2040BB4; Wed, 3 Apr 2013 11:19:03 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by axis700.grange (Postfix) with ESMTP id 650DD40BB3; Wed, 3 Apr 2013 11:19:03 +0200 (CEST) Date: Wed, 3 Apr 2013 11:19:03 +0200 (CEST) From: Guennadi Liakhovetski X-X-Sender: lyakh@axis700.grange To: Simon Horman Subject: [PATCH/RFC 1/2] irqchip: renesas-intc-irqpin: DT binding for sense bitfield width In-Reply-To: Message-ID: References: MIME-Version: 1.0 X-Provags-ID: V02:K0:GCO+8WJLOJABhYeyC445NqTjmz4XyYMvBymwj5OFOoc Ny6FDHuup36AHAtPCJARIkM+ewzk80GgE5SLrgGjefaLlAv10L 7es/6m11Uvaz5hP2u5bfVU462dcK5ELYnVgjUYyVkY1mw++qjy CuAHgvjOmVgu4BXbSjg8HBKWstbGccGCxOaJQg50bqvuiQ+srE KcWT7MPlCWG5xM2I7qKNX9/DB0HMbr1ksKl2zP2/Pya8oHYT7w ZBZwVFc3aywiyXXajwhPAAdBCZF6zCt5uWO19x9qAvndiDtmBT 2bbRL0QHITbBc72YCPOI1prxCgvZrLgjHSvpEFhNevi4fML5AZ YvKr1GkndcDqhR9jzZpG5kRDW4rTHJdI8OUSk1my6PPlX1VSio mmTiqSlzJ/fHA== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130403_051909_436489_64E596A2 X-CRM114-Status: GOOD ( 11.99 ) X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [212.227.17.9 listed in list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (g.liakhovetski[at]gmx.de) -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record -2.3 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: devicetree-discuss@lists.ozlabs.org, Magnus Damm , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, linux-sh@vger.kernel.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Most Renesas irqpin controllers have 4-bit sense fields, however, some have different widths. This patch adds a DT binding to optionally specify such non-standard values. Signed-off-by: Guennadi Liakhovetski --- .../interrupt-controller/renesas,intc-irqpin.txt | 2 ++ drivers/irqchip/irq-renesas-intc-irqpin.c | 5 ++++- 2 files changed, 6 insertions(+), 1 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt index e55d183..6b48742 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt @@ -11,3 +11,5 @@ Optional properties: resource allocation properties - control-parent: disable and enable interrupts on the parent interrupt controller, needed for some broken implementations +- sense-bitfield-width: width of a single sense bitfield in the SENSE register, + if different from the default 4 bits diff --git a/drivers/irqchip/irq-renesas-intc-irqpin.c b/drivers/irqchip/irq-renesas-intc-irqpin.c index 82bbe8f..6aadfe6 100644 --- a/drivers/irqchip/irq-renesas-intc-irqpin.c +++ b/drivers/irqchip/irq-renesas-intc-irqpin.c @@ -381,9 +381,12 @@ static int intc_irqpin_probe(struct platform_device *pdev) for (k = 0; k < p->number_of_irqs; k++) intc_irqpin_mask_unmask_prio(p, k, 1); - if (!pdata) + if (!pdata) { p->config.control_parent = of_property_read_bool(pdev->dev.of_node, "control-parent"); + of_property_read_u32(pdev->dev.of_node, "sense-bitfield-width", + &p->config.sense_bitfield_width); + } /* use more severe masking method if requested */ if (p->config.control_parent) {