From patchwork Sun Jul 25 04:25:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= X-Patchwork-Id: 12397977 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_ADSP_ALL,DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA184C4338F for ; Sun, 25 Jul 2021 04:28:11 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9A24260E77 for ; Sun, 25 Jul 2021 04:28:11 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 9A24260E77 Authentication-Results: mail.kernel.org; dmarc=fail (p=reject dis=none) header.from=rere.qmqm.pl Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:MIME-Version:Subject:From: References:In-Reply-To:Message-Id:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=gznRK26TDECYMpsb7XvLq4x1Y8r7wFN08Wn8N3rK67c=; b=R9w/ZswsZfqcf48MzMRFyvQB+M L8/Hfsp3y8okyMAI9Ahjxj/h4N92CZD+o95wtddkeut6e0EJfbLxB9sUj4YB0EmTqV7oRr0TygnFW WRNJgjuOdaS/yXdM2XLS+QkQbtAujRfchl1drG4UVBMh5HELZOjEwcesXKBDHGFWYnCkKJ9ZCQB36 deHyHNGqVudsLh+UsXNFMQVbE/I0soZwKLapKJyp2nUo42vUIDcXiDs9NKwGVUPIlFq2BlJlfqJP/ BNXVekW4yb/qAt7W8tfLesBDUr76zkvkqkipAWoeB33p09FLCXkyXZ1ocZsmyFZn0b5AUf6P6vO0U Ey4y6JzA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m7ViR-00891y-SB; Sun, 25 Jul 2021 04:26:16 +0000 Received: from rere.qmqm.pl ([91.227.64.183]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1m7Vha-0088wv-Eo for linux-arm-kernel@lists.infradead.org; Sun, 25 Jul 2021 04:25:24 +0000 Received: from remote.user (localhost [127.0.0.1]) by rere.qmqm.pl (Postfix) with ESMTPSA id 4GXVMy2jlHzwg; Sun, 25 Jul 2021 06:25:18 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=rere.qmqm.pl; s=1; t=1627187118; bh=7aLr1DcvH9n5VyrTP2IaJJvojTP4sCPPtY6zdO/RZU4=; h=Date:In-Reply-To:References:From:Subject:To:Cc:From; b=r0gQ6/bSunpdszUfoQuNTcVee1+16h6NzOT8R42K8/M7tmbIW9SSYZdaoN6hK2Iul ZzT4iWpFbi317/8LKsc4s/6pdoWne+aeleBHPc132bIgkRBg/9YkM1TQeQLsGf7Ikk FDg6uEYLu4oKXaD/v47SMAu+7e8JN00b0GEsOP4JL7B2iAx9iUQ7d6eo07ZYRLZksF Lj9eHf16vt7WbnanwuQvBBqfHZ18e2I4xBglZuT92xGie9rfidbdYGfIQUB6IuHXTl KRkN1FnFAk1ZY111zi4iqDhAi/D7CY2DVtr/3z45SVE92xBmY0Pf2wpglNLsb2ryh6 MR+Frz3u98UNw== X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.2 at mail Date: Sun, 25 Jul 2021 06:25:18 +0200 Message-Id: In-Reply-To: References: From: =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= Subject: [PATCH v3 5/5] mmc: sdhci: simplify v2/v3+ clock calculation MIME-Version: 1.0 To: Kevin Liu , Suneel Garapati , Ulf Hansson Cc: Adrian Hunter , Chris Ball , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, Michal Simek X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210724_212522_903286_388E3B6C X-CRM114-Status: GOOD ( 18.95 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org For base clock setting, SDHCI V2 differs from V3+ only in allowed divisor values. Remove the duplicate version of code and reduce indentation levels. We can see now, that 'real_div' can't be zero, so the check is removed. While at it, replace divisor search loops with divide-and-clamp to make the code even more readable. Signed-off-by: Michał Mirosław --- v3: squashed div-conversion and deduplication patches to avoid code churn v2: no changes --- drivers/mmc/host/sdhci.c | 124 ++++++++++++++++++--------------------- drivers/mmc/host/sdhci.h | 4 +- 2 files changed, 58 insertions(+), 70 deletions(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index cfa314e659bc..90bda4150083 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1848,88 +1848,76 @@ static u16 sdhci_get_preset_value(struct sdhci_host *host) u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, unsigned int *actual_clock) { - int div = 0; /* Initialized for compiler warning */ - int real_div = div, clk_mul = 1; + unsigned int div, real_div, clk_mul = 1; u16 clk = 0; - bool switch_base_clk = false; - if (host->version >= SDHCI_SPEC_300) { - if (host->preset_enabled) { - u16 pre_val; + if (clock == 0) + return clk; + + if (host->preset_enabled) { + /* Only version 3.00+ can have preset_enabled */ + u16 pre_val; + + pre_val = sdhci_get_preset_value(host); + div = FIELD_GET(SDHCI_PRESET_SDCLK_FREQ_MASK, pre_val); + if (!(pre_val & SDHCI_PRESET_CLKGEN_SEL)) + goto base_div_set; + + clk = SDHCI_PROG_CLOCK_MODE; + real_div = div + 1; + clk_mul = host->clk_mul; + if (!clk_mul) { + /* The clock frequency is unknown. Assume undivided base. */ + clk_mul = 1; + } + + goto clock_set; + } + + /* + * Check if the Host Controller supports Programmable Clock + * Mode. + */ + if (host->version >= SDHCI_SPEC_300 && host->clk_mul) { + div = DIV_ROUND_UP(host->max_clk * host->clk_mul, clock); + if (div <= SDHCI_MAX_DIV_SPEC_300 / 2 + 1) { + /* + * Set Programmable Clock Mode in the Clock + * Control register. + */ + clk = SDHCI_PROG_CLOCK_MODE; + clk_mul = host->clk_mul; + real_div = div--; - pre_val = sdhci_get_preset_value(host); - div = FIELD_GET(SDHCI_PRESET_SDCLK_FREQ_MASK, pre_val); - if (pre_val & SDHCI_PRESET_CLKGEN_SEL) { - clk = SDHCI_PROG_CLOCK_MODE; - real_div = div + 1; - clk_mul = host->clk_mul; - if (!clk_mul) { - /* The clock frequency is unknown. Assume undivided base. */ - clk_mul = 1; - } - } else { - real_div = max_t(int, 1, div << 1); - } goto clock_set; } /* - * Check if the Host Controller supports Programmable Clock - * Mode. + * Divisor is too big for requested clock rate. + * Fall back to the base clock. */ - if (host->clk_mul) { - for (div = 1; div <= 1024; div++) { - if ((host->max_clk * host->clk_mul / div) - <= clock) - break; - } - if ((host->max_clk * host->clk_mul / div) <= clock) { - /* - * Set Programmable Clock Mode in the Clock - * Control register. - */ - clk = SDHCI_PROG_CLOCK_MODE; - real_div = div; - clk_mul = host->clk_mul; - div--; - } else { - /* - * Divisor can be too small to reach clock - * speed requirement. Then use the base clock. - */ - switch_base_clk = true; - } - } + } - if (!host->clk_mul || switch_base_clk) { - /* Version 3.00 divisors must be a multiple of 2. */ - if (host->max_clk <= clock) { - div = 1; - if (host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN) - div = 2; - } else { - for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; - div += 2) { - if ((host->max_clk / div) <= clock) - break; - } - } - real_div = div; - div >>= 1; - } + div = DIV_ROUND_UP(host->max_clk, clock); + + if (div == 1 && (host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)) + div = 2; + + if (host->version >= SDHCI_SPEC_300) { + /* Version 3.00 divisors must be a multiple of 2. */ + div = min(div, SDHCI_MAX_DIV_SPEC_300); + div = DIV_ROUND_UP(div, 2); } else { /* Version 2.00 divisors must be a power of 2. */ - for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { - if ((host->max_clk / div) <= clock) - break; - } - real_div = div; - div >>= 1; + div = min(div, SDHCI_MAX_DIV_SPEC_200); + div = roundup_pow_of_two(div) / 2; } +base_div_set: + real_div = div * 2 + !div; + clock_set: - if (real_div) - *actual_clock = (host->max_clk * clk_mul) / real_div; + *actual_clock = (host->max_clk * clk_mul) / real_div; clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) << SDHCI_DIVIDER_HI_SHIFT; diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 074dc182b184..a3fa70d91410 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -284,8 +284,8 @@ * End of controller registers. */ -#define SDHCI_MAX_DIV_SPEC_200 256 -#define SDHCI_MAX_DIV_SPEC_300 2046 +#define SDHCI_MAX_DIV_SPEC_200 256u +#define SDHCI_MAX_DIV_SPEC_300 2046u /* * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.