From patchwork Mon Apr 11 18:45:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Baruch Siach X-Patchwork-Id: 12809490 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 86D90C433F5 for ; Mon, 11 Apr 2022 18:47:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=bp/F6SuoJwAFrykhwdd+5QDNzs7kcqOHw9sHMlykaTM=; b=bRVb6Ar4/+xXRj M+fLWIkgXvaoOL7+/9Kc2yfHtBizDZRdOi7pGoZJQO/+M9h33gunj+233lwugEOrj85TyX3Fr3gwA OFPzoWvAqVc4O9/pv57xKUNtqohapFieZ7YIG3UsdbnPZyMQIa0f0kznkeKcIhRnCI4+Tud+sSJHE BJKrvE8uc01otArElQaTiIZRMHGltSIJCXK2NYWBMG6NEDFPTFIjxD2FiWmcAg+KjM6ptwkfLTI8O lam8I6KMOvgMVQ5XX1kN8ly03amHP6AG7MHWxJJDwwuPDet3kdyDC5Yy+AVpTbpsKAwi9WN9CDk17 16+0ioIXCS0rF9Uty0MQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ndz3X-00AEQY-DG; Mon, 11 Apr 2022 18:46:31 +0000 Received: from wiki.tkos.co.il ([84.110.109.230] helo=mail.tkos.co.il) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ndz3L-00AEOV-DB for linux-arm-kernel@lists.infradead.org; Mon, 11 Apr 2022 18:46:21 +0000 Received: from tarshish.tkos.co.il (unknown [10.0.8.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.tkos.co.il (Postfix) with ESMTPS id 62411440850; Mon, 11 Apr 2022 21:45:39 +0300 (IDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=tkos.co.il; s=default; t=1649702739; bh=A46Vf+O4fgj2Kf0M0kC0BdmGePrGz2TiFZvx75W3cnA=; h=From:To:Cc:Subject:Date:From; b=N2g2iTk0YcZJ/fbTR48Cllipjd9yWh5Z2VbR7YoraOYNZokky2pSj5r5/AGYd+xbx oHWY87iNCDMm8Kec2KLrigF3pKvbN6zGq1zixtwjamXAL7wFEuEeJVjUUJn9ksGnff xbIoCYUmdXr118yy3HOHPjqMWb5xko7sPOG86P1rtV8kQro2HZ0P7WzmWzJYL5lN6c sAh0327dKc9JrZuLFeAw6+6sz+AfvUQjwRtvSbfkQWwt0XBiF9Lv7B6mO3QpMNW47A q3AVtybBpE9oh+qVf4b1nlOYybBWV4uJ7RGrjNCrJUAmQO4bibd21CuEYcqRDVEWrp igLKj0tcHNpDA== From: Baruch Siach To: Mark Brown Cc: Baruch Siach , linux-spi@vger.kernel.org, Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/3] spi: add SPI_RX_CPHA_FLIP mode bit Date: Mon, 11 Apr 2022 21:45:27 +0300 Message-Id: X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220411_114619_879365_95FE4450 X-CRM114-Status: GOOD ( 13.25 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Baruch Siach Some SPI devices latch MOSI bits on one clock phase, but produce valid MISO bits on the other phase. Add SPI_RX_CPHA_FLIP mode to instruct the controller driver to flip CPHA for Rx (MISO) only transfers. Signed-off-by: Baruch Siach --- include/uapi/linux/spi/spi.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/uapi/linux/spi/spi.h b/include/uapi/linux/spi/spi.h index 236a85f08ded..9d5f58059703 100644 --- a/include/uapi/linux/spi/spi.h +++ b/include/uapi/linux/spi/spi.h @@ -27,6 +27,7 @@ #define SPI_TX_OCTAL _BITUL(13) /* transmit with 8 wires */ #define SPI_RX_OCTAL _BITUL(14) /* receive with 8 wires */ #define SPI_3WIRE_HIZ _BITUL(15) /* high impedance turnaround */ +#define SPI_RX_CPHA_FLIP _BITUL(16) /* flip CPHA on Rx only xfer */ /* * All the bits defined above should be covered by SPI_MODE_USER_MASK. @@ -36,6 +37,6 @@ * These bits must not overlap. A static assert check should make sure of that. * If adding extra bits, make sure to increase the bit index below as well. */ -#define SPI_MODE_USER_MASK (_BITUL(16) - 1) +#define SPI_MODE_USER_MASK (_BITUL(17) - 1) #endif /* _UAPI_SPI_H */