diff mbox series

[4/5] arm64: dts: renesas: r8a779g0: Add CPU core clocks

Message ID aa6e9ae21e451ebd40d54d986bd0296571128d5b.1668429870.git.geert+renesas@glider.be (mailing list archive)
State New, archived
Headers show
Series arm64: dts: renesas: r8a779g0: CPU topology improvements | expand

Commit Message

Geert Uytterhoeven Nov. 14, 2022, 12:49 p.m. UTC 
Describe the clocks for the four Cortex-A76 CPU cores.
CA76 Sub-Systems 0/1 (both clusters / all CPU cores) are clocked by Z0φ.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 4 ++++
 1 file changed, 4 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
index 21baa4936b4fba3e..9cbe337220ed4dfc 100644
--- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
@@ -46,6 +46,7 @@  a76_0: cpu@0 {
 			next-level-cache = <&L3_CA76_0>;
 			enable-method = "psci";
 			cpu-idle-states = <&CPU_SLEEP_0>;
+			clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>;
 		};
 
 		a76_1: cpu@100 {
@@ -56,6 +57,7 @@  a76_1: cpu@100 {
 			next-level-cache = <&L3_CA76_0>;
 			enable-method = "psci";
 			cpu-idle-states = <&CPU_SLEEP_0>;
+			clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>;
 		};
 
 		a76_2: cpu@10000 {
@@ -66,6 +68,7 @@  a76_2: cpu@10000 {
 			next-level-cache = <&L3_CA76_1>;
 			enable-method = "psci";
 			cpu-idle-states = <&CPU_SLEEP_0>;
+			clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>;
 		};
 
 		a76_3: cpu@10100 {
@@ -76,6 +79,7 @@  a76_3: cpu@10100 {
 			next-level-cache = <&L3_CA76_1>;
 			enable-method = "psci";
 			cpu-idle-states = <&CPU_SLEEP_0>;
+			clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>;
 		};
 
 		idle-states {