From patchwork Wed Nov 22 14:42:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Baruch Siach X-Patchwork-Id: 10070535 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3BC07601D5 for ; Wed, 22 Nov 2017 14:44:44 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2A37B29C5C for ; Wed, 22 Nov 2017 14:44:44 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1E96029C78; Wed, 22 Nov 2017 14:44:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C4CCC29C5C for ; Wed, 22 Nov 2017 14:44:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=ODjCOhiiG6c3UbE1bX7R5xdwFcOpqLn76crzkfFsPvA=; b=RniZJOzsZXNzagrbnEd64U9XpL GUXU+0DF94t0ZupfOFZQZjkAud6lSPIj3Nwh+AeYNWJhM/8t/4k4rdsQNtJqnVPDe95e+f5uktHcC 9kh7NCIani6Y1V5qd5Ak2y148AmVu4kZiGQTH++Os2aFVcsHNyuyI6HZaPYXPFQb+kOUexJvEtQDq XJOOSeg/XqOikEckg14Q9RLDuxg2X4j/4Ix/BQM5BBdFnCFExdbtdAl1/WmTaHqJgP+0WYmhVrhTl wQaxl/vYKIvWVwqY9XpGkhtjQORfgcKIWzn0ks0l3aUx4xfja+qk8x8wXZyA6wHMvvWvOa7vN7RTF wLMD3r6w==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1eHWGQ-0004lW-IL; Wed, 22 Nov 2017 14:44:34 +0000 Received: from guitar.tcltek.co.il ([192.115.133.116] helo=mx.tkos.co.il) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1eHWFU-0003se-1N for linux-arm-kernel@lists.infradead.org; Wed, 22 Nov 2017 14:43:40 +0000 Received: from sapphire.lan (unknown [10.0.4.3]) by mx.tkos.co.il (Postfix) with ESMTPA id 91247440A0A; Wed, 22 Nov 2017 16:43:08 +0200 (IST) From: Baruch Siach To: Zhang Rui , Eduardo Valentin Subject: [PATCH 3/3] thermal: armada: add support for CP110 Date: Wed, 22 Nov 2017 16:42:05 +0200 Message-Id: X-Mailer: git-send-email 2.15.0 In-Reply-To: <7102bb32704ac9f70ef3ae61682d50de8af61b57.1511361725.git.baruch@tkos.co.il> References: <7102bb32704ac9f70ef3ae61682d50de8af61b57.1511361725.git.baruch@tkos.co.il> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20171122_064336_451335_C7DB7C2A X-CRM114-Status: GOOD ( 12.10 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Lunn , Baruch Siach , Jason Cooper , linux-pm@vger.kernel.org, Miquel Raynal , Gregory Clement , linux-arm-kernel@lists.infradead.org, Sebastian Hesselbarth MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The CP110 component is integrated in the Armada 8k and 7k lines of processors. This patch also adds an option of offset to the MSB of the control register. The existing DT binding for Armada 38x refers to a single 32 bit control register. It turns out that this is actually only the MSB of the control area. Changing the binding to fix that would break existing DT files, so the Armada 38x binding is left as is. The new CP110 binding increases the size of the control area to 64 bits, thus moving the MSB to offset 4. Signed-off-by: Baruch Siach --- drivers/thermal/armada_thermal.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/thermal/armada_thermal.c b/drivers/thermal/armada_thermal.c index 1f7f81628040..542db578ce36 100644 --- a/drivers/thermal/armada_thermal.c +++ b/drivers/thermal/armada_thermal.c @@ -72,6 +72,7 @@ struct armada_thermal_data { unsigned int temp_shift; unsigned int temp_mask; unsigned int is_valid_shift; + unsigned int control_msb_offset; }; static void armadaxp_init_sensor(struct platform_device *pdev, @@ -141,12 +142,14 @@ static void armada375_init_sensor(struct platform_device *pdev, static void armada380_init_sensor(struct platform_device *pdev, struct armada_thermal_priv *priv) { - unsigned long reg = readl_relaxed(priv->control); + void __iomem *control_msb = + priv->control + priv->data->control_msb_offset; + unsigned long reg = readl_relaxed(control_msb); /* Reset hardware once */ if (!(reg & A380_HW_RESET)) { reg |= A380_HW_RESET; - writel(reg, priv->control); + writel(reg, control_msb); mdelay(10); } } @@ -258,6 +261,19 @@ static const struct armada_thermal_data armada_ap806_data = { .inverted = true, }; +static const struct armada_thermal_data armada_cp110_data = { + .is_valid = armada_is_valid, + .init_sensor = armada380_init_sensor, + .is_valid_shift = 10, + .temp_shift = 0, + .temp_mask = 0x3ff, + .control_msb_offset = 4, + .coef_b = 1172499100UL, + .coef_m = 2000096UL, + .coef_div = 4201, + .inverted = true, +}; + static const struct of_device_id armada_thermal_id_table[] = { { .compatible = "marvell,armadaxp-thermal", @@ -279,6 +295,10 @@ static const struct of_device_id armada_thermal_id_table[] = { .compatible = "marvell,armada-ap806-thermal", .data = &armada_ap806_data, }, + { + .compatible = "marvell,armada-cp110-thermal", + .data = &armada_cp110_data, + }, { /* sentinel */ },