From patchwork Sat Jul 27 04:10:56 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Walmsley X-Patchwork-Id: 2834582 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 8167E9F4E2 for ; Sat, 27 Jul 2013 04:11:34 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9481620169 for ; Sat, 27 Jul 2013 04:11:33 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9C39720168 for ; Sat, 27 Jul 2013 04:11:32 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V2vqo-0007ug-PX; Sat, 27 Jul 2013 04:11:27 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1V2vqm-0000Wq-Fy; Sat, 27 Jul 2013 04:11:24 +0000 Received: from utopia.booyaka.com ([74.50.51.50]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V2vqj-0000WX-0s for linux-arm-kernel@lists.infradead.org; Sat, 27 Jul 2013 04:11:22 +0000 Received: (qmail 4880 invoked by uid 1019); 27 Jul 2013 04:10:56 -0000 Date: Sat, 27 Jul 2013 04:10:56 +0000 (UTC) From: Paul Walmsley To: Will Deacon Subject: Re: OMAP2430 SDP boot broken after Linus' rmk merge In-Reply-To: <20130724142059.GJ11072@mudshark.cambridge.arm.com> Message-ID: References: <20130722184325.GA21614@n2100.arm.linux.org.uk> <51EE2AA7.5060503@ti.com> <51EE474D.5070804@ti.com> <20130724135617.GI11072@mudshark.cambridge.arm.com> <51EFE1DD.8070801@ti.com> <20130724142059.GJ11072@mudshark.cambridge.arm.com> User-Agent: Alpine 2.02 (DEB 1266 2009-07-14) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130727_001121_155824_EDD1E491 X-CRM114-Status: UNSURE ( 9.54 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -1.9 (-) Cc: Russell King - ARM Linux , "linux-omap@vger.kernel.org" , Rajendra Nayak , Santosh Shilimkar , "linux-arm-kernel@lists.infradead.org" X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Tonight I put on a Jon Hopkins album, in recollection of my UK ARM Linux colleagues perhaps, and started testing, and eventually wound up with this one: commit 621a0147d5c921f4cc33636ccd0602ad5d7cbfbc Author: Will Deacon Date: Wed Jun 12 12:25:56 2013 +0100 ARM: 7757/1: mm: don't flush icache in switch_mm with hardware broadcasting When scheduling an mm on a CPU where it hasn't previously been used, we flush the icache on that CPU so that any code loaded previously on a different core can be safely executed. For cores with hardware broadcasting of cache maintenance operations, this is clearly unnecessary, since the inner-shareable invalidation in __sync_icache_dcache will affect all CPUs. This patch conditionalises the icache flush in switch_mm based on cache_ops_need_broadcast(). Acked-by: Catalin Marinas Reported-by: Albin Tonnerre Signed-off-by: Will Deacon Signed-off-by: Russell King ... v3.11-rc2 boots with it reverted. What also works is v3.11-rc2 with the below patch applied. Would be pleased to boot-test anything you'd care to send my way, as long as you can tolerate response latency jitter. - Paul diff --git a/arch/arm/include/asm/mmu_context.h b/arch/arm/include/asm/mmu_context.h index b5792b7..8dfb295 100644 --- a/arch/arm/include/asm/mmu_context.h +++ b/arch/arm/include/asm/mmu_context.h @@ -112,7 +112,7 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next, * so check for possible thread migration and invalidate the I-cache * if we're new to this CPU. */ - if (cache_ops_need_broadcast() && + if (1 && !cpumask_empty(mm_cpumask(next)) && !cpumask_test_cpu(cpu, mm_cpumask(next))) __flush_icache_all();