From patchwork Sun Jul 28 05:43:24 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Walmsley X-Patchwork-Id: 2834669 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E3951C0319 for ; Sun, 28 Jul 2013 05:43:56 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id BBFF72013D for ; Sun, 28 Jul 2013 05:43:55 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B5D5520138 for ; Sun, 28 Jul 2013 05:43:54 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V3Jln-0005GL-3n; Sun, 28 Jul 2013 05:43:51 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1V3Jlk-0004k4-Tg; Sun, 28 Jul 2013 05:43:48 +0000 Received: from utopia.booyaka.com ([74.50.51.50]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V3Jlh-0004j9-VF for linux-arm-kernel@lists.infradead.org; Sun, 28 Jul 2013 05:43:46 +0000 Received: (qmail 26350 invoked by uid 1019); 28 Jul 2013 05:43:24 -0000 Date: Sun, 28 Jul 2013 05:43:24 +0000 (UTC) From: Paul Walmsley To: Will Deacon Subject: [PATCH] ARM: v6: avoid read_cpuid_ext() on ARM1136r0 in cache_ops_need_broadcast() In-Reply-To: <20130727122221.GB6618@mudshark.cambridge.arm.com> Message-ID: References: <20130722184325.GA21614@n2100.arm.linux.org.uk> <51EE2AA7.5060503@ti.com> <51EE474D.5070804@ti.com> <20130724135617.GI11072@mudshark.cambridge.arm.com> <51EFE1DD.8070801@ti.com> <20130724142059.GJ11072@mudshark.cambridge.arm.com> <20130727122221.GB6618@mudshark.cambridge.arm.com> User-Agent: Alpine 2.02 (DEB 1266 2009-07-14) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130728_014346_090557_96A309D3 X-CRM114-Status: GOOD ( 17.29 ) X-Spam-Score: -1.9 (-) Cc: Russell King - ARM Linux , "linux-omap@vger.kernel.org" , Rajendra Nayak , Santosh Shilimkar , "linux-arm-kernel@lists.infradead.org" X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Commit 621a0147d5c921f4cc33636ccd0602ad5d7cbfbc ("ARM: 7757/1: mm: don't flush icache in switch_mm with hardware broadcasting") breaks the boot on OMAP2430SDP with omap2plus_defconfig. Tracked to an undefined instruction abort from the CP15 read in cache_ops_need_broadcast(). It turns out that early ARM1136 variants don't support several CP15 registers that later ARM cores do. ARM1136JF-S TRM section 3.2.1 "Register allocation" has the details. So, prevent cache_ops_need_broadcast() from attempting the CP15 read if the running CPU doesn't provide the register. cache_ops_need_broadcast() is a hot path function, so focus on minimizing the execution time impact. A subsequent patch will take care of the remaining cases in the current kernel. Thanks to Will Deacon for helping track this down. Signed-off-by: Paul Walmsley Cc: Will Deacon --- Intended for v3.11-rc. Tested (along with the followup patch) here: http://www.pwsan.com/omap/testlogs/bisect_2430sdp_hang_v3.11-rc/20130727224434/README.txt against stock v3.11-rc2, so several boards aren't booting due to unrelated issues. arch/arm/include/asm/cputype.h | 37 ++++++++++++++++++++++++++++++++++++- arch/arm/include/asm/smp_plat.h | 4 +++- 2 files changed, 39 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h index 8c25dc4..91ccd77 100644 --- a/arch/arm/include/asm/cputype.h +++ b/arch/arm/include/asm/cputype.h @@ -76,6 +76,8 @@ #define ARM_CPU_XSCALE_ARCH_V2 0x4000 #define ARM_CPU_XSCALE_ARCH_V3 0x6000 +#define ARM_CPU_ARM1136R0 0x4107b360 + extern unsigned int processor_id; #ifdef CONFIG_CPU_CP15 @@ -89,10 +91,43 @@ extern unsigned int processor_id; __val; \ }) + +/* Workaround for missing CP15 registers on ARM1136 r0 */ +# if defined(CONFIG_CPU_V6) +/** + * cpu_is_arm1136_r0 - is the kernel running on an ARM1136 r0 core? + * + * Returns true if the kernel is running on an ARM1136 r0 core, or + * false otherwise. Callers use this to avoid undefined instruction + * aborts from CP15 accesses to registers not present on the r0 + * variant, or to detect whether certain CPU features are available. + * ARM1136JF-S TRM section 3.2.1 "Register allocation" + */ +static inline bool __attribute_const__ cpu_is_arm1136_r0(void) +{ + return ((read_cpuid(CPUID_ID) & 0xfffffff0) == ARM_CPU_ARM1136R0); +} + +/* + * The mrc in the read_cpuid_ext macro must not be reordered on ARMv6, + * else the compiler may move it before any ARM1136r0 test. + */ +# define CPUID_EXT_REORDER volatile +# else +static inline bool __attribute_const__ cpu_is_arm1136_r0(void) { return false; } +# define CPUID_EXT_REORDER +# endif + +/* + * Early ARM1136 variants don't support many CP15 registers provided + * on later cores. Users of read_cpuid_ext must ensure that it won't + * be used unless it's known that the running core provides the CP15 + * register ext_reg. See cpu_is_arm1136_r0() above. + */ #define read_cpuid_ext(ext_reg) \ ({ \ unsigned int __val; \ - asm("mrc p15, 0, %0, c0, " ext_reg \ + asm CPUID_EXT_REORDER("mrc p15, 0, %0, c0, " ext_reg \ : "=r" (__val) \ : \ : "cc"); \ diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h index 6462a72..76214cb 100644 --- a/arch/arm/include/asm/smp_plat.h +++ b/arch/arm/include/asm/smp_plat.h @@ -25,7 +25,6 @@ static inline bool is_smp(void) #endif } -/* all SMP configurations have the extended CPUID registers */ #ifndef CONFIG_MMU #define tlb_ops_need_broadcast() 0 #else @@ -43,6 +42,9 @@ static inline int tlb_ops_need_broadcast(void) #else static inline int cache_ops_need_broadcast(void) { + if (cpu_is_arm1136_r0()) + return 0; + if (!is_smp()) return 0;