From patchwork Sun Jul 28 20:16:29 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Walmsley X-Patchwork-Id: 2834725 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 42FB0C0319 for ; Sun, 28 Jul 2013 20:17:02 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5B30020127 for ; Sun, 28 Jul 2013 20:17:01 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3DBE620126 for ; Sun, 28 Jul 2013 20:17:00 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V3XOi-0005kS-8p; Sun, 28 Jul 2013 20:16:56 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1V3XOf-0007I3-TO; Sun, 28 Jul 2013 20:16:53 +0000 Received: from utopia.booyaka.com ([74.50.51.50]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V3XOc-0007H4-He for linux-arm-kernel@lists.infradead.org; Sun, 28 Jul 2013 20:16:51 +0000 Received: (qmail 27205 invoked by uid 1019); 28 Jul 2013 20:16:29 -0000 Date: Sun, 28 Jul 2013 20:16:29 +0000 (UTC) From: Paul Walmsley To: Russell King - ARM Linux , Will Deacon Subject: [PATCH] ARM: v6: prevent gcc from reordering extended CP15 reads above is_smp() test In-Reply-To: Message-ID: References: <20130722184325.GA21614@n2100.arm.linux.org.uk> <51EE2AA7.5060503@ti.com> <51EE474D.5070804@ti.com> <20130724135617.GI11072@mudshark.cambridge.arm.com> <51EFE1DD.8070801@ti.com> <20130724142059.GJ11072@mudshark.cambridge.arm.com> <20130727122221.GB6618@mudshark.cambridge.arm.com> User-Agent: Alpine 2.02 (DEB 1266 2009-07-14) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130728_161650_801318_8C340C94 X-CRM114-Status: GOOD ( 12.89 ) X-Spam-Score: -1.9 (-) Cc: "linux-omap@vger.kernel.org" , Rajendra Nayak , Santosh Shilimkar , "linux-arm-kernel@lists.infradead.org" X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Commit 621a0147d5c921f4cc33636ccd0602ad5d7cbfbc ("ARM: 7757/1: mm: don't flush icache in switch_mm with hardware broadcasting") breaks the boot on OMAP2430SDP with omap2plus_defconfig. Tracked to an undefined instruction abort from the CP15 read in cache_ops_need_broadcast(). It turns out that gcc reorders the extended CP15 read above the is_smp() test. This breaks ARM1136 r0 cores, since they don't support several CP15 registers that later ARM cores do. ARM1136JF-S TRM section 3.2.1 "Register allocation" has the details. So, when the kernel is built for ARMv6 cores, mark the extended CP15 read as clobbering memory, which seems to prevent the compiler from reordering it before the is_smp() test. Russell states that the code generated from this approach is preferable to marking the inline asm as volatile. This patch was developed in collaboration with Will Deacon and Russell King. Signed-off-by: Paul Walmsley Cc: Will Deacon Cc: Russell King Acked-by: Tony Lindgren --- Thought I'd respin this to have a discussion strawman. It boots cleanly on 2430SDP. [ Updated "ARM: v6: avoid read_cpuid_ext() on ARM1136r0 in cache_ops_need_broadcast()" to drop the unnecessary ARM1136 r0 test, to switch to a memory clobber per rmk's suggestion, and to update the commit message. ] Intended for v3.11-rc. arch/arm/include/asm/cputype.h | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h index 8c25dc4..f428eb0 100644 --- a/arch/arm/include/asm/cputype.h +++ b/arch/arm/include/asm/cputype.h @@ -89,13 +89,25 @@ extern unsigned int processor_id; __val; \ }) + +# if defined(CONFIG_CPU_V6) +/* + * The mrc in the read_cpuid_ext macro must not be reordered on ARMv6, + * else the compiler may move it before an is_smp() test, causing + * undefined instruction aborts on ARM1136 r0. + */ +# define CPUID_EXT_REORDER "cc", "memory" +# else +# define CPUID_EXT_REORDER "cc" +# endif + #define read_cpuid_ext(ext_reg) \ ({ \ unsigned int __val; \ asm("mrc p15, 0, %0, c0, " ext_reg \ : "=r" (__val) \ : \ - : "cc"); \ + : CPUID_EXT_REORDER); \ __val; \ })