From patchwork Wed Aug 14 14:25:14 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolas Pitre X-Patchwork-Id: 2844614 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 425ADBF546 for ; Wed, 14 Aug 2013 14:25:52 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id ED8DB204D3 for ; Wed, 14 Aug 2013 14:25:50 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7FC3420178 for ; Wed, 14 Aug 2013 14:25:49 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V9c19-00083B-Kg; Wed, 14 Aug 2013 14:25:43 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1V9c17-0002fM-Fu; Wed, 14 Aug 2013 14:25:41 +0000 Received: from mail-qa0-f49.google.com ([209.85.216.49]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V9c15-0002ef-1J for linux-arm-kernel@lists.infradead.org; Wed, 14 Aug 2013 14:25:39 +0000 Received: by mail-qa0-f49.google.com with SMTP id cr7so1090650qab.1 for ; Wed, 14 Aug 2013 07:25:17 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-gm-message-state:date:from:to:cc:subject:in-reply-to:message-id :references:user-agent:mime-version:content-type; bh=6vHbxpGLH1UZZEzBqkD45bL6023a7h0v2MLyTUzOYpQ=; b=FhQC3N1MB3eHLsjTqdL7kz05PEhc6bK3Bg5TwCb7g3aA/VeBUjm34lnjvNjj85nM5q l6eyRMSTSir6eLr7IrtbTu+5r5hFqgKMKBZOrPtpaftE3FTXPzXZmxmuX9BTj/3fvEIt GMGLGWwM/z92ZCKg2bPylDbFFvRKqeXtUwPix+GyBsmd0Tgm09reKR3z57uA/Re8bMXL cYRmSLwtENBD5r0EoukfZek8Fs5xn4DYRVVEIq05ghlSHFFuB99Cap2KiPZ6zdmwhqxx nVhWUvAeJiIBEa6+uyJsNr3DDGiGCSA/gVIQmmVzhNZCQ/GjoX6fWAk/h2YYKD6fF5+8 d37g== X-Gm-Message-State: ALoCoQmqEUPcoP6QRtyw8GLYR35kIbJFlWdnWohmpNcTFqhZ2nhh8PPQs0r7szRB8YOV1dcsmxcY X-Received: by 10.49.74.102 with SMTP id s6mr12003572qev.24.1376490316621; Wed, 14 Aug 2013 07:25:16 -0700 (PDT) Received: from xanadu.home (modemcable044.209-83-70.mc.videotron.ca. [70.83.209.44]) by mx.google.com with ESMTPSA id e5sm11776592qae.9.2013.08.14.07.25.15 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 14 Aug 2013 07:25:16 -0700 (PDT) Date: Wed, 14 Aug 2013 10:25:14 -0400 (EDT) From: Nicolas Pitre To: Olof Johansson Subject: Re: [Git pull request] fix to the vexpress/mcpm branch In-Reply-To: <20130814055800.GG16635@quad.lixom.net> Message-ID: References: <20130814055800.GG16635@quad.lixom.net> User-Agent: Alpine 2.03 (LFD 1266 2009-07-14) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130814_102539_154201_2E050226 X-CRM114-Status: GOOD ( 18.65 ) X-Spam-Score: -2.6 (--) Cc: lorenzo.pieralisi@arm.com, khilman@linaro.org, pawel.moll@arm.com, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-7.0 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Tue, 13 Aug 2013, Olof Johansson wrote: > Hi Nico, > > On Mon, Aug 12, 2013 at 02:37:54PM -0400, Nicolas Pitre wrote: > > > > Please pull the following: > > > > git://git.linaro.org/people/nico/linux mcpm+tc2 > > > > which will update your vexpress/mcpm branch with one additional commit > > fixing the build issue with CONFIG_FRAME_POINTER reported by RMK. This > > commit's SHA1 is 95fbdc9cf542. > > So, I just replaced my branch with the one from Pawel, and the topmost patch > in your branch seems to no longer apply. Weird. It still applies perfectly here. Here's the patch nevertheless. Please apply ASAP as Lorenzo wishes to base his next pull request on top of this. ----- >8 From: Nicolas Pitre Date: Mon, 12 Aug 2013 12:47:13 -0400 Subject: [PATCH] ARM: vexpress/MCPM: fix cache disable sequence when CONFIG_FRAME_POINTER=y If CONFIG_FRAME_POINTER=y we hget the following error: arch/arm/mach-vexpress/tc2_pm.c: In function 'tc2_pm_down': arch/arm/mach-vexpress/tc2_pm.c:200:1: error: fp cannot be used in asm here Let's fix that by explicitly preserving r11 on the stack and removing it from the clobber list. Reported-by: Russell King Reviewed-by: Dave Martin Signed-off-by: Nicolas Pitre diff --git a/arch/arm/mach-vexpress/dcscb.c b/arch/arm/mach-vexpress/dcscb.c index 85fffa702f..3a6384c6c4 100644 --- a/arch/arm/mach-vexpress/dcscb.c +++ b/arch/arm/mach-vexpress/dcscb.c @@ -144,8 +144,13 @@ static void dcscb_power_down(void) * Let's do it in the safest possible way i.e. with * no memory access within the following sequence * including to the stack. + * + * Note: fp is preserved to the stack explicitly prior doing + * this since adding it to the clobber list is incompatible + * with having CONFIG_FRAME_POINTER=y. */ asm volatile( + "str fp, [sp, #-4]! \n\t" "mrc p15, 0, r0, c1, c0, 0 @ get CR \n\t" "bic r0, r0, #"__stringify(CR_C)" \n\t" "mcr p15, 0, r0, c1, c0, 0 @ set CR \n\t" @@ -156,9 +161,10 @@ static void dcscb_power_down(void) "bic r0, r0, #(1 << 6) @ disable local coherency \n\t" "mcr p15, 0, r0, c1, c0, 1 @ set AUXCR \n\t" "isb \n\t" - "dsb " + "dsb \n\t" + "ldr fp, [sp], #4" : : : "r0","r1","r2","r3","r4","r5","r6","r7", - "r9","r10","r11","lr","memory"); + "r9","r10","lr","memory"); /* * This is a harmless no-op. On platforms with a real @@ -182,6 +188,7 @@ static void dcscb_power_down(void) * Let's do it in the safest possible way as above. */ asm volatile( + "str fp, [sp, #-4]! \n\t" "mrc p15, 0, r0, c1, c0, 0 @ get CR \n\t" "bic r0, r0, #"__stringify(CR_C)" \n\t" "mcr p15, 0, r0, c1, c0, 0 @ set CR \n\t" @@ -192,9 +199,10 @@ static void dcscb_power_down(void) "bic r0, r0, #(1 << 6) @ disable local coherency \n\t" "mcr p15, 0, r0, c1, c0, 1 @ set AUXCR \n\t" "isb \n\t" - "dsb " + "dsb \n\t" + "ldr fp, [sp], #4" : : : "r0","r1","r2","r3","r4","r5","r6","r7", - "r9","r10","r11","lr","memory"); + "r9","r10","lr","memory"); } __mcpm_cpu_down(cpu, cluster); diff --git a/arch/arm/mach-vexpress/tc2_pm.c b/arch/arm/mach-vexpress/tc2_pm.c index ddd97dd4e9..2b7c93a724 100644 --- a/arch/arm/mach-vexpress/tc2_pm.c +++ b/arch/arm/mach-vexpress/tc2_pm.c @@ -150,8 +150,13 @@ static void tc2_pm_down(u64 residency) * Let's do it in the safest possible way i.e. with * no memory access within the following sequence * including the stack. + * + * Note: fp is preserved to the stack explicitly prior doing + * this since adding it to the clobber list is incompatible + * with having CONFIG_FRAME_POINTER=y. */ asm volatile( + "str fp, [sp, #-4]! \n\t" "mrc p15, 0, r0, c1, c0, 0 @ get CR \n\t" "bic r0, r0, #"__stringify(CR_C)" \n\t" "mcr p15, 0, r0, c1, c0, 0 @ set CR \n\t" @@ -162,9 +167,10 @@ static void tc2_pm_down(u64 residency) "bic r0, r0, #(1 << 6) @ disable local coherency \n\t" "mcr p15, 0, r0, c1, c0, 1 @ set AUXCR \n\t" "isb \n\t" - "dsb " + "dsb \n\t" + "ldr fp, [sp], #4" : : : "r0","r1","r2","r3","r4","r5","r6","r7", - "r9","r10","r11","lr","memory"); + "r9","r10","lr","memory"); cci_disable_port_by_cpu(mpidr); @@ -185,6 +191,7 @@ static void tc2_pm_down(u64 residency) * Let's do it in the safest possible way as above. */ asm volatile( + "str fp, [sp, #-4]! \n\t" "mrc p15, 0, r0, c1, c0, 0 @ get CR \n\t" "bic r0, r0, #"__stringify(CR_C)" \n\t" "mcr p15, 0, r0, c1, c0, 0 @ set CR \n\t" @@ -195,9 +202,10 @@ static void tc2_pm_down(u64 residency) "bic r0, r0, #(1 << 6) @ disable local coherency \n\t" "mcr p15, 0, r0, c1, c0, 1 @ set AUXCR \n\t" "isb \n\t" - "dsb " + "dsb \n\t" + "ldr fp, [sp], #4" : : : "r0","r1","r2","r3","r4","r5","r6","r7", - "r9","r10","r11","lr","memory"); + "r9","r10","lr","memory"); } __mcpm_cpu_down(cpu, cluster);