From patchwork Tue Jul 28 23:43:20 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolas Pitre X-Patchwork-Id: 6888741 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id D99FF9F39D for ; Tue, 28 Jul 2015 23:46:31 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C641320770 for ; Tue, 28 Jul 2015 23:46:30 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8D4F320755 for ; Tue, 28 Jul 2015 23:46:29 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZKEXD-00039o-Oe; Tue, 28 Jul 2015 23:43:47 +0000 Received: from mail-qk0-f169.google.com ([209.85.220.169]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZKEXB-00038O-1u for linux-arm-kernel@lists.infradead.org; Tue, 28 Jul 2015 23:43:46 +0000 Received: by qkbm65 with SMTP id m65so58622236qkb.2 for ; Tue, 28 Jul 2015 16:43:22 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:date:from:to:cc:subject:message-id:user-agent :mime-version:content-type; bh=oFpPq05gujhCw9Cro5E9gegkz6Lk3ZsjdT22gdln7tU=; b=ZpcKblrrq7ZFq3lIDi+swB38crUIhY73fyxmJorEbmDzenDdPFjNZW+egfibSMCmvj SKb4fvsi23/8r2p9FxazWguQFsqdJSzlTV8A4aYiAAUGgUUYE352TthkvXNRvnAYJUn6 YAwbgueXD4P7Nmsy84pojagxrDX9240TVXuKGiircV+yu7Ep6ixKGUZMnrxgBGdQsH6/ mHhydIR7KOxuEeYZZxuQkB9yetmNr2ya4JDlcvs0NXjVbKlwpKrt6MrUhVnRtWkoQkKP 5dYPvL7NO9hXvmp5Hm8hs8y7GPSPRWP/+MZUF0SDq6Z178N/6NfazrKKnA/dac86Nbi/ YY4Q== X-Gm-Message-State: ALoCoQnTs+5mD41074SHM9sckrhQBKCA1q/Xt/Cjk68HBJBr3ECBvNv9PTVLL48lbUpmtMuhOHb4 X-Received: by 10.55.22.170 with SMTP id 42mr53921163qkw.71.1438127002677; Tue, 28 Jul 2015 16:43:22 -0700 (PDT) Received: from xanadu.home (modemcable065.157-23-96.mc.videotron.ca. [96.23.157.65]) by smtp.gmail.com with ESMTPSA id c89sm9747570qga.36.2015.07.28.16.43.21 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 28 Jul 2015 16:43:21 -0700 (PDT) Date: Tue, 28 Jul 2015 19:43:20 -0400 (EDT) From: Nicolas Pitre To: Michael Turquette Subject: [PATCH] drivers/clk: appropriate __init annotation for const data Message-ID: User-Agent: Alpine 2.20 (LFD 67 2015-01-07) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150728_164345_183293_4D692549 X-CRM114-Status: GOOD ( 12.03 ) X-Spam-Score: -2.6 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Init data marked const should be annotated with __initconst for correctness and not __initdata. This also fixes LTO builds that otherwise fail with section mismatch errors. Signed-off-by: Nicolas Pitre diff --git a/drivers/clk/clk-asm9260.c b/drivers/clk/clk-asm9260.c index 90897af8d9..25308ce09a 100644 --- a/drivers/clk/clk-asm9260.c +++ b/drivers/clk/clk-asm9260.c @@ -244,10 +244,10 @@ static const struct asm9260_gate_data asm9260_ahb_gates[] __initconst = { HW_AHBCLKCTRL1, 16 }, }; -static const char __initdata *main_mux_p[] = { NULL, NULL }; -static const char __initdata *i2s0_mux_p[] = { NULL, NULL, "i2s0m_div"}; -static const char __initdata *i2s1_mux_p[] = { NULL, NULL, "i2s1m_div"}; -static const char __initdata *clkout_mux_p[] = { NULL, NULL, "rtc"}; +static const char *const main_mux_p[] __initconst = { NULL, NULL }; +static const char *const i2s0_mux_p[] __initconst = { NULL, NULL, "i2s0m_div"}; +static const char *const i2s1_mux_p[] __initconst = { NULL, NULL, "i2s1m_div"}; +static const char *const clkout_mux_p[] __initconst = { NULL, NULL, "rtc"}; static u32 three_mux_table[] = {0, 1, 3}; static struct asm9260_mux_clock asm9260_mux_clks[] __initdata = { diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c index 3f6f7ad394..c316454ef8 100644 --- a/drivers/clk/clk-stm32f4.c +++ b/drivers/clk/clk-stm32f4.c @@ -293,7 +293,7 @@ stm32f4_rcc_lookup_clk(struct of_phandle_args *clkspec, void *data) return clks[i]; } -static const char *sys_parents[] __initdata = { "hsi", NULL, "pll" }; +static const char *const sys_parents[] __initconst = { "hsi", NULL, "pll" }; static const struct clk_div_table ahb_div_table[] = { { 0x0, 1 }, { 0x1, 1 }, { 0x2, 1 }, { 0x3, 1 }, diff --git a/drivers/clk/hisilicon/clk-hi6220.c b/drivers/clk/hisilicon/clk-hi6220.c index 4563343b64..d7c7d73bd3 100644 --- a/drivers/clk/hisilicon/clk-hi6220.c +++ b/drivers/clk/hisilicon/clk-hi6220.c @@ -91,23 +91,23 @@ CLK_OF_DECLARE(hi6220_clk_ao, "hisilicon,hi6220-aoctrl", hi6220_clk_ao_init); /* clocks in sysctrl */ -static const char *mmc0_mux0_p[] __initdata = { "pll_ddr_gate", "syspll", }; -static const char *mmc0_mux1_p[] __initdata = { "mmc0_mux0", "pll_media_gate", }; -static const char *mmc0_src_p[] __initdata = { "mmc0srcsel", "mmc0_div", }; -static const char *mmc1_mux0_p[] __initdata = { "pll_ddr_gate", "syspll", }; -static const char *mmc1_mux1_p[] __initdata = { "mmc1_mux0", "pll_media_gate", }; -static const char *mmc1_src_p[] __initdata = { "mmc1srcsel", "mmc1_div", }; -static const char *mmc2_mux0_p[] __initdata = { "pll_ddr_gate", "syspll", }; -static const char *mmc2_mux1_p[] __initdata = { "mmc2_mux0", "pll_media_gate", }; -static const char *mmc2_src_p[] __initdata = { "mmc2srcsel", "mmc2_div", }; -static const char *mmc0_sample_in[] __initdata = { "mmc0_sample", "mmc0_pad", }; -static const char *mmc1_sample_in[] __initdata = { "mmc1_sample", "mmc1_pad", }; -static const char *mmc2_sample_in[] __initdata = { "mmc2_sample", "mmc2_pad", }; -static const char *uart1_src[] __initdata = { "clk_tcxo", "clk_150m", }; -static const char *uart2_src[] __initdata = { "clk_tcxo", "clk_150m", }; -static const char *uart3_src[] __initdata = { "clk_tcxo", "clk_150m", }; -static const char *uart4_src[] __initdata = { "clk_tcxo", "clk_150m", }; -static const char *hifi_src[] __initdata = { "syspll", "pll_media_gate", }; +static const char *const mmc0_mux0_p[] __initconst = { "pll_ddr_gate", "syspll", }; +static const char *const mmc0_mux1_p[] __initconst = { "mmc0_mux0", "pll_media_gate", }; +static const char *const mmc0_src_p[] __initconst = { "mmc0srcsel", "mmc0_div", }; +static const char *const mmc1_mux0_p[] __initconst = { "pll_ddr_gate", "syspll", }; +static const char *const mmc1_mux1_p[] __initconst = { "mmc1_mux0", "pll_media_gate", }; +static const char *const mmc1_src_p[] __initconst = { "mmc1srcsel", "mmc1_div", }; +static const char *const mmc2_mux0_p[] __initconst = { "pll_ddr_gate", "syspll", }; +static const char *const mmc2_mux1_p[] __initconst = { "mmc2_mux0", "pll_media_gate", }; +static const char *const mmc2_src_p[] __initconst = { "mmc2srcsel", "mmc2_div", }; +static const char *const mmc0_sample_in[] __initconst = { "mmc0_sample", "mmc0_pad", }; +static const char *const mmc1_sample_in[] __initconst = { "mmc1_sample", "mmc1_pad", }; +static const char *const mmc2_sample_in[] __initconst = { "mmc2_sample", "mmc2_pad", }; +static const char *const uart1_src[] __initconst = { "clk_tcxo", "clk_150m", }; +static const char *const uart2_src[] __initconst = { "clk_tcxo", "clk_150m", }; +static const char *const uart3_src[] __initconst = { "clk_tcxo", "clk_150m", }; +static const char *const uart4_src[] __initconst = { "clk_tcxo", "clk_150m", }; +static const char *const hifi_src[] __initconst = { "syspll", "pll_media_gate", }; static struct hisi_gate_clock hi6220_separated_gate_clks_sys[] __initdata = { { HI6220_MMC0_CLK, "mmc0_clk", "mmc0_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 0, 0, }, @@ -197,9 +197,9 @@ CLK_OF_DECLARE(hi6220_clk_sys, "hisilicon,hi6220-sysctrl", hi6220_clk_sys_init); /* clocks in media controller */ -static const char *clk_1000_1200_src[] __initdata = { "pll_gpu_gate", "media_syspll_src", }; -static const char *clk_1440_1200_src[] __initdata = { "media_syspll_src", "media_pll_src", }; -static const char *clk_1000_1440_src[] __initdata = { "pll_gpu_gate", "media_pll_src", }; +static const char *const clk_1000_1200_src[] __initconst = { "pll_gpu_gate", "media_syspll_src", }; +static const char *const clk_1440_1200_src[] __initconst = { "media_syspll_src", "media_pll_src", }; +static const char *const clk_1000_1440_src[] __initconst = { "pll_gpu_gate", "media_pll_src", }; static struct hisi_gate_clock hi6220_separated_gate_clks_media[] __initdata = { { HI6220_DSI_PCLK, "dsi_pclk", "vpucodec", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 0, 0, }, diff --git a/drivers/clk/versatile/clk-realview.c b/drivers/clk/versatile/clk-realview.c index c8b523117f..0c1f224515 100644 --- a/drivers/clk/versatile/clk-realview.c +++ b/drivers/clk/versatile/clk-realview.c @@ -33,13 +33,13 @@ static const struct icst_params realview_oscvco_params = { .idx2s = icst307_idx2s, }; -static const struct clk_icst_desc __initdata realview_osc0_desc = { +static const struct clk_icst_desc realview_osc0_desc __initconst = { .params = &realview_oscvco_params, .vco_offset = REALVIEW_SYS_OSC0_OFFSET, .lock_offset = REALVIEW_SYS_LOCK_OFFSET, }; -static const struct clk_icst_desc __initdata realview_osc4_desc = { +static const struct clk_icst_desc realview_osc4_desc __initconst = { .params = &realview_oscvco_params, .vco_offset = REALVIEW_SYS_OSC4_OFFSET, .lock_offset = REALVIEW_SYS_LOCK_OFFSET, diff --git a/drivers/clk/versatile/clk-versatile.c b/drivers/clk/versatile/clk-versatile.c index 7a4f8635bd..81d59eada2 100644 --- a/drivers/clk/versatile/clk-versatile.c +++ b/drivers/clk/versatile/clk-versatile.c @@ -35,7 +35,7 @@ static const struct icst_params cp_auxosc_params = { .idx2s = icst525_idx2s, }; -static const struct clk_icst_desc __initdata cm_auxosc_desc = { +static const struct clk_icst_desc cm_auxosc_desc __initconst = { .params = &cp_auxosc_params, .vco_offset = 0x1c, .lock_offset = INTEGRATOR_HDR_LOCK_OFFSET,