From patchwork Wed Nov 18 17:01:06 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolas Pitre X-Patchwork-Id: 7651091 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id BD0799F392 for ; Wed, 18 Nov 2015 17:03:57 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C6F0F205B1 for ; Wed, 18 Nov 2015 17:03:56 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CA803205AA for ; Wed, 18 Nov 2015 17:03:55 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Zz66v-0001b3-HM; Wed, 18 Nov 2015 17:01:33 +0000 Received: from relais.videotron.ca ([24.201.245.36]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Zz66s-0001XT-4A for linux-arm-kernel@lists.infradead.org; Wed, 18 Nov 2015 17:01:30 +0000 MIME-version: 1.0 Received: from yoda.home ([96.23.157.65]) by VL-VM-MR002.ip.videotron.ca (Oracle Communications Messaging Exchange Server 7u4-22.01 64bit (built Apr 21 2011)) with ESMTP id <0NY000897SLUGH90@VL-VM-MR002.ip.videotron.ca> for linux-arm-kernel@lists.infradead.org; Wed, 18 Nov 2015 12:01:06 -0500 (EST) Received: from xanadu.home (xanadu.home [192.168.2.2]) by yoda.home (Postfix) with ESMTPSA id 4E1282DA01E3; Wed, 18 Nov 2015 12:01:06 -0500 (EST) Date: Wed, 18 Nov 2015 12:01:06 -0500 (EST) From: Nicolas Pitre To: Magnus Damm Subject: Re: [PATCH v3] ARM: xip: Use correct symbol for end of ROM marker In-reply-to: Message-id: References: <1447362108-4333-1-git-send-email-chris.brandt@renesas.com> <1447697140-4099-1-git-send-email-chris.brandt@renesas.com> User-Agent: Alpine 2.20 (LFD 67 2015-01-07) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151118_090130_261689_6587A3CA X-CRM114-Status: GOOD ( 16.45 ) X-Spam-Score: -2.6 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Chris Brandt , "linux@arm.linux.org.uk" , "linux-arm-kernel@lists.infradead.org" , "linux-sh@vger.kernel.org" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Wed, 18 Nov 2015, Nicolas Pitre wrote: > On Wed, 18 Nov 2015, Magnus Damm wrote: > > > Thanks for your take on this. I did a couple of local implementations > > before submitting, and one of the issues I ran into was the need to > > get rid of PAGE_OFFSET due to the code running without MMU enabled. I > > suppose that is taken care of the "__v7_setup_stack - ." calculation > > above? > > Yes. That provides the offset from __v7_setup_stack_ptr to reach > __v7_setup_stack. And __v7_setup_stack_ptr is obtained with adr which is > relative to the current pc. So this works whether or not the MMU is > enabled. Here's the patch with proper changelog, etc. I don't have XIP capable hardware to test it with though. ------ >8 From: Nicolas Pitre Subject: [PATCH] ARM: proc-v7*.S: don't locate temporary stack space in .text section Both proc-v7.S and proc-v7m.S are using a small temporary stack to preserve register content within their respective setup code. This stack is located in the .text section which is normally meant to be read-only. This is even more true in the context of an XIP kernel where .text is accessed from ROM directly. Move that temporary stack to the .bss section and get its address in a position independent way. While at it, one comments was updated to reflect reality, and the list of saved registers in the proc-v7.S case is updated to match the comment next to it for coherency. Signed-off-by: Nicolas Pitre Signed-off-by: Nicolas Pitre diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index de2b246fed..2d0ac32320 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -274,10 +274,12 @@ __v7_ca15mp_setup: __v7_b15mp_setup: __v7_ca17mp_setup: mov r10, #0 -1: adr r12, __v7_setup_stack @ the local stack - stmia r12, {r0-r5, lr} @ v7_invalidate_l1 touches r0-r6 +1: adr r0, __v7_setup_stack_ptr + ldr r12, [r0] + add r12, r12, r0 @ the local stack + stmia r12, {r1-r6, lr} @ v7_invalidate_l1 touches r0-r6 bl v7_invalidate_l1 - ldmia r12, {r0-r5, lr} + ldmia r12, {r1-r6, lr} #ifdef CONFIG_SMP ALT_SMP(mrc p15, 0, r0, c1, c0, 1) ALT_UP(mov r0, #(1 << 6)) @ fake it for UP @@ -415,10 +417,12 @@ __v7_pj4b_setup: #endif /* CONFIG_CPU_PJ4B */ __v7_setup: - adr r12, __v7_setup_stack @ the local stack - stmia r12, {r0-r5, lr} @ v7_invalidate_l1 touches r0-r6 + adr r0, __v7_setup_stack_ptr + ldr r12, [r0] + add r12, r12, r0 @ the local stack + stmia r12, {r1-r6, lr} @ v7_invalidate_l1 touches r0-r6 bl v7_invalidate_l1 - ldmia r12, {r0-r5, lr} + ldmia r12, {r1-r6, lr} __v7_setup_cont: and r0, r9, #0xff000000 @ ARM? @@ -480,11 +484,16 @@ __errata_finish: orr r0, r0, r6 @ set them THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions ret lr @ return to head.S:__ret + + .align 2 +__v7_setup_stack_ptr: + .word __v7_setup_stack - . ENDPROC(__v7_setup) + .bss .align 2 __v7_setup_stack: - .space 4 * 7 @ 12 registers + .space 4 * 7 @ 7 registers __INITDATA diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S index 67d9209077..8cd465927a 100644 --- a/arch/arm/mm/proc-v7m.S +++ b/arch/arm/mm/proc-v7m.S @@ -123,10 +123,12 @@ __v7m_setup: ret lr ENDPROC(__v7m_setup) + .pushsection .bss .align 2 __v7m_setup_stack: .space 4 * 8 @ 8 registers __v7m_setup_stack_top: + .previous define_processor_functions v7m, dabort=nommu_early_abort, pabort=legacy_pabort, nommu=1