From patchwork Tue Oct 6 22:32:38 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Duc Dang X-Patchwork-Id: 7340531 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 6E4B29F1B9 for ; Tue, 6 Oct 2015 22:36:33 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8576D20695 for ; Tue, 6 Oct 2015 22:36:32 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B03F820606 for ; Tue, 6 Oct 2015 22:36:31 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Zjanp-0006fC-EP; Tue, 06 Oct 2015 22:33:45 +0000 Received: from mail-pa0-x22a.google.com ([2607:f8b0:400e:c03::22a]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Zjanm-0006Y2-R9 for linux-arm-kernel@lists.infradead.org; Tue, 06 Oct 2015 22:33:43 +0000 Received: by pablk4 with SMTP id lk4so221562128pab.3 for ; Tue, 06 Oct 2015 15:33:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=apm.com; s=apm; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=EREDiNeOaBUzWR2AwU7Sfllu+DyNArb9QJvkaMLGQvQ=; b=cr9u7ad1fsyUiFmk4awIWYmK+JRf9Un1eQgddYnzjlPEuLlxJ+MGxnN1lnD8Zkc9f9 2vrVNbr6/8Mz8VGsDET10jJ5+J327CQJN6jvKHlCzPw1tGYLytwQ2FE2jv9BEymSxTyZ hltdZdbmpJK1wjQmhjkkGOTokM2uxejSf9Vx4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=EREDiNeOaBUzWR2AwU7Sfllu+DyNArb9QJvkaMLGQvQ=; b=UqekPykMouIKPb53lUy7wv9XyHJuWOR34H5yqL6Ubi9APtimO1lPGdecZhePfKaAlk 37gMQy+x/Vt6RY3IgV8wj7BjvWDwS7fbsrQjjNmBYG5H3ePuSwfyBgQvXnbLhplYkKfN iKVzBRYqfgZsg2Um2L2ulGW36tuJLTdG/cp+dXVHxYGGGRUaLISNpM2A7l3MOwyghWHw /kw9HD6qINUE42fb3qVYcWJ4WdhH5qDnxHHj5ZFT1bbO47g+UCmCBmp4kqLL6VY/B/yZ gjTW9B9Qn4FGLJ8cXNIvlFe+F+ZpbtkyAJBo32ANlX4CV0m9cVvQzHE8d8u04aSaMnOC sd5g== X-Gm-Message-State: ALoCoQmmzxS91D1hGnGbrjZQu+vOXk2PFXJIOxEYWCYOoECOynf6DdwfhPU12WolDd7knZaAgJY+ X-Received: by 10.68.222.163 with SMTP id qn3mr18748154pbc.54.1444170801893; Tue, 06 Oct 2015 15:33:21 -0700 (PDT) Received: from dhdang-Precision-WorkStation-T3400.amcc.com (70-35-53-82.static.wiline.com. [70.35.53.82]) by smtp.gmail.com with ESMTPSA id be6sm35597044pad.5.2015.10.06.15.33.20 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 06 Oct 2015 15:33:21 -0700 (PDT) From: Duc Dang To: Marc Zyngier , Suravee Suthikulpanit , Jason Cooper , Thomas Gleixner Subject: [PATCH v2 1/1] irqchip/GICv2m: Add workaround for APM X-Gene GICv2m erratum Date: Tue, 6 Oct 2015 15:32:38 -0700 Message-Id: X-Mailer: git-send-email 1.9.1 In-Reply-To: <20151003142650.16b291b4@arm.com> References: <20151003142650.16b291b4@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151006_153342_918474_449EBB93 X-CRM114-Status: GOOD ( 18.23 ) X-Spam-Score: -2.7 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Duc Dang , patches@apm.com, linux-kernel@vger.kernel.org, linux-arm MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP APM X-Gene GICv2m implementation has an erratum where the MSI data needs to be the offset from the spi_start in order to trigger the correct MSI interrupt. This is different from the standard GICv2m implementation where the MSI data is the absolute value within the range from spi_start to (spi_start + num_spis) of each v2m frame. This patch reads MSI_IIDR register (present in all GICv2m implementations) to identify X-Gene GICv2m implementation and apply workaround to change the data portion of MSI vector. Signed-off-by: Duc Dang Reviewed-by: Marc Zyngier --- Changes since v1: + Group V2M_MSI_IIDR definition to V2M register group + Set v2m flag during init to indicate the erratum and use that flag to manipulate the MSI data when composing MSI msg. drivers/irqchip/irq-gic-v2m.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/irqchip/irq-gic-v2m.c b/drivers/irqchip/irq-gic-v2m.c index db04fc1..4c17c18 100644 --- a/drivers/irqchip/irq-gic-v2m.c +++ b/drivers/irqchip/irq-gic-v2m.c @@ -37,12 +37,19 @@ #define V2M_MSI_SETSPI_NS 0x040 #define V2M_MIN_SPI 32 #define V2M_MAX_SPI 1019 +#define V2M_MSI_IIDR 0xFCC #define V2M_MSI_TYPER_BASE_SPI(x) \ (((x) >> V2M_MSI_TYPER_BASE_SHIFT) & V2M_MSI_TYPER_BASE_MASK) #define V2M_MSI_TYPER_NUM_SPI(x) ((x) & V2M_MSI_TYPER_NUM_MASK) +/* APM X-Gene with GICv2m MSI_IIDR register value */ +#define XGENE_GICV2M_MSI_IIDR 0x06000170 + +/* List of flags for specific v2m implementation */ +#define GICV2M_NEEDS_SPI_OFFSET 0x00000001 + struct v2m_data { spinlock_t msi_cnt_lock; struct resource res; /* GICv2m resource */ @@ -50,6 +57,7 @@ struct v2m_data { u32 spi_start; /* The SPI number that MSIs start */ u32 nr_spis; /* The number of SPIs for MSIs */ unsigned long *bm; /* MSI vector bitmap */ + u32 flags; /* v2m flags for specific implementation */ }; static void gicv2m_mask_msi_irq(struct irq_data *d) @@ -98,6 +106,9 @@ static void gicv2m_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) msg->address_hi = (u32) (addr >> 32); msg->address_lo = (u32) (addr); msg->data = data->hwirq; + + if (v2m->flags & GICV2M_NEEDS_SPI_OFFSET) + msg->data -= v2m->spi_start; } static struct irq_chip gicv2m_irq_chip = { @@ -266,6 +277,17 @@ static int __init gicv2m_init_one(struct device_node *node, goto err_iounmap; } + /* + * APM X-Gene GICv2m implementation has an erratum where + * the MSI data needs to be the offset from the spi_start + * in order to trigger the correct MSI interrupt. This is + * different from the standard GICv2m implementation where + * the MSI data is the absolute value within the range from + * spi_start to (spi_start + num_spis). + */ + if (readl_relaxed(v2m->base + V2M_MSI_IIDR) == XGENE_GICV2M_MSI_IIDR) + v2m->flags |= GICV2M_NEEDS_SPI_OFFSET; + v2m->bm = kzalloc(sizeof(long) * BITS_TO_LONGS(v2m->nr_spis), GFP_KERNEL); if (!v2m->bm) {