From patchwork Tue Dec 14 16:27:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Baruch Siach X-Patchwork-Id: 12696087 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 478DCC433F5 for ; Tue, 14 Dec 2021 16:29:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=g+F2mfxI+GUdRKlTwYW1lO5tWbIV+SQHf9IJfAAaGT0=; b=37dTxc73f1FlXr ue+bv7zIJ5/2EHflpOfnpVYxlyHFBt0dg3ZuFbdy6IvFHksw0cqqKxEBPs1A9Z1UVTGBFvQyBGSiL +y8wJL3Rqtvw8ej0V6QK3kN+9FlIJd9bAlFtIZPArTQ5dMGVxGDXK/LkKqG4Cr8owziiWtU/go+09 8+eDXbbxI5JgjpmjNRKsPZBAj+j7plpdfuJR+bxxuKlhEc7YSoP/+X3ju+IqeexA7ftyvr1rE857n pKJR0i79vWCNQiL0qhch3MXyVQuaNVmdXGduFy1/lNFeKWRtCl6lBiKKiTUbO16MqVu4lbctHtz/D HIUeMQWxXzoYYNcWZNFg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mxAer-00EroZ-L3; Tue, 14 Dec 2021 16:28:05 +0000 Received: from guitar.tcltek.co.il ([84.110.109.230] helo=mx.tkos.co.il) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mxAen-00Ermo-N1 for linux-arm-kernel@lists.infradead.org; Tue, 14 Dec 2021 16:28:03 +0000 Received: from tarshish.tkos.co.il (unknown [10.0.8.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mx.tkos.co.il (Postfix) with ESMTPS id 0327F440F34; Tue, 14 Dec 2021 18:27:58 +0200 (IST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=tkos.co.il; s=default; t=1639499279; bh=9Rw5Mc29eN/o9vijCYUqBWAJbdad6p8H0eoU63ST/UY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=be/HCnusCrpatssrHQVih54osJxacCWYSPGPdquy6P8Oz87KUH1PnzNtpRJ4IKBLM 2P/V4X5S6+sl0cmxqAiPjMAPNUDWQADHhuuY1R341P54BSj1z7PQpGV5YD6ShHsR+l qNk7shtHzWVb/9Oc9gNrORdvoBNKa/RXa5+OdFza/qQ1uHebY/d1wbNUd8sYiAi1PP N8kmJJKkYFqIQTKPaxuOqIrbQ29JGTANUWpT+IfkgKw128vwKajM2p68ei6Me/1WMZ HrXxkGhq9TdFrOQ67HgR99jnL/ja8+tAcEUbgUg1j8Y4aHQLUKc1UY4zfWyaTq+s57 klGbmuBJdeXKA== From: Baruch Siach To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6n?= =?utf-8?q?ig?= , Andy Gross , Bjorn Andersson Cc: Baruch Siach , Balaji Prakash J , Rob Herring , Robert Marko , Kathiravan T , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v10 2/3] dt-bindings: pwm: add IPQ6018 binding Date: Tue, 14 Dec 2021 18:27:18 +0200 Message-Id: X-Mailer: git-send-email 2.33.0 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211214_082802_209243_BB672870 X-CRM114-Status: GOOD ( 14.94 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Baruch Siach DT binding for the PWM block in Qualcomm IPQ6018 SoC. Signed-off-by: Baruch Siach --- This series does not convert the TCSR binding documentation to YAML. As a result, this commit adds new a dt_binding_check warning: /example-0/syscon@1937000: failed to match any schema with compatible: ['qcom,tcsr-ipq 6018', 'syscon', 'simple-mfd'] If that is a blocker to IPQ6018 PWM support, so be it. Patches will wait for someone else to push them further. v10: No change v9: Add 'ranges' property to example (Rob) Drop label in example (Rob) v8: Add size cell to 'reg' (Rob) v7: Use 'reg' instead of 'offset' (Rob) Drop 'clock-names' and 'assigned-clock*' (Bjorn) Use single cell address/size in example node (Bjorn) Move '#pwm-cells' lower in example node (Bjorn) List 'reg' as required v6: Device node is child of TCSR; remove phandle (Rob Herring) Add assigned-clocks/assigned-clock-rates (Uwe Kleine-König) v5: Use qcom,pwm-regs for phandle instead of direct regs (Bjorn Andersson, Kathiravan T) v4: Update the binding example node as well (Rob Herring's bot) v3: s/qcom,pwm-ipq6018/qcom,ipq6018-pwm/ (Rob Herring) v2: Make #pwm-cells const (Rob Herring) --- .../devicetree/bindings/pwm/ipq-pwm.yaml | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/ipq-pwm.yaml diff --git a/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml b/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml new file mode 100644 index 000000000000..857086ad539e --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/ipq-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm IPQ6018 PWM controller + +maintainers: + - Baruch Siach + +properties: + "#pwm-cells": + const: 2 + + compatible: + const: qcom,ipq6018-pwm + + reg: + description: Offset of PWM register in the TCSR block. + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - "#pwm-cells" + +additionalProperties: false + +examples: + - | + #include + + syscon@1937000 { + compatible = "qcom,tcsr-ipq6018", "syscon", "simple-mfd"; + reg = <0x01937000 0x21000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1937000 0x21000>; + + pwm: pwm@a010 { + compatible = "qcom,ipq6018-pwm"; + reg = <0xa010 0x20>; + clocks = <&gcc GCC_ADSS_PWM_CLK>; + assigned-clocks = <&gcc GCC_ADSS_PWM_CLK>; + assigned-clock-rates = <100000000>; + #pwm-cells = <2>; + }; + };