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Thu, 28 Mar 2024 23:15:16 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.9) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Thu, 28 Mar 2024 23:15:15 -0700 From: Nicolin Chen To: , CC: , , , , , , , , Subject: [PATCH v4 3/6] iommu/arm-smmu-v3: Make __arm_smmu_cmdq_skip_err reusable Date: Thu, 28 Mar 2024 23:14:07 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF0000449E:EE_|IA1PR12MB6092:EE_ X-MS-Office365-Filtering-Correlation-Id: 70dc324b-dbe7-4e88-60d9-08dc4fb7a1b4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 7MF2ou5YM9FgbRGYjKg2kvI3gOHUDmb+YStlSLZ2SwbxuMGJ9UeoCdlStNXsk5CxlA0AEeXAo5Ne01EOpdPHaSMD0vN542lJOOW7EYaHnLE2vvj70bUE5Acnp1iHSpzv9oBrr/sjKTGdwfRRRB6BwRoYDCUKk3/G72gRnho7eqbDqBYudRdksNe0kWqcPvxDIR/VAjRSQ7i02lY/IOPCq6/59uf49D/yQJyCQcKgSKtKYhfbBT3p1De3NZT6h/Lw0MSs8Dan+s3Nfzht/W25eQsDvamd2tn87VDvkFHe3LMXQNtQWIBm3Ir8ueBZFq9bBaqQSzK7r28yC3TqM5BYr998sVi9KikB1XCKmzyCw5xLwhlSk4be9EI6BU28jD/oZ4rHLOWVigTHHzGbseY3aSYdDsAysehsEBgScMmKKjSgBHsVSga+M9o5OZzmfxzLHhfwEia8WdaSOyQBn7OzGX7Auc6+5TLcJR6l3flM05dQwQ11t2OkFaPx/5xLJVcihDoeAwnXRMKjo3pWSRJ0TsJURKZ988RbSAA6y2NWukUfIKxGw9xx7wv4+5O6E4XnctX32zT1tQzjvwekVLRVKVayEDvZlgrS1LMqWVBxLHdKEEkg04Mj8JnJ1NDqcmtyxrHjjHqFwOBb311SPcxwYn5nz6XBTFyeJwUbnqvV19ZoXqrGG3KsE2aTrBPaHubJZytTX2gjG5ZWrw6IVk1MVqXUItjb8B+1XM0PNNJM8aDnC5nKqWcE/6DeIiq0Tnzv X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230031)(376005)(82310400014)(1800799015)(36860700004);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Mar 2024 06:15:28.8455 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 70dc324b-dbe7-4e88-60d9-08dc4fb7a1b4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF0000449E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6092 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240328_231536_354562_16CA5FE6 X-CRM114-Status: GOOD ( 12.63 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Allow __arm_smmu_cmdq_skip_err function to be reused by NVIDIA Tegra241 CMDQV unit since it will use the same data structure for q. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 16 +++++++++------- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 44fcc0c0a149..6cb20bff5a8a 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -379,8 +379,7 @@ static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu, arm_smmu_cmdq_build_cmd(cmd, &ent); } -static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, - struct arm_smmu_queue *q) +void __arm_smmu_cmdq_skip_err(struct device *dev, struct arm_smmu_queue *q) { static const char * const cerror_str[] = { [CMDQ_ERR_CERROR_NONE_IDX] = "No error", @@ -397,12 +396,12 @@ static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, .opcode = CMDQ_OP_CMD_SYNC, }; - dev_err(smmu->dev, "CMDQ error (cons 0x%08x): %s\n", cons, + dev_err(dev, "CMDQ error (cons 0x%08x): %s\n", cons, idx < ARRAY_SIZE(cerror_str) ? cerror_str[idx] : "Unknown"); switch (idx) { case CMDQ_ERR_CERROR_ABT_IDX: - dev_err(smmu->dev, "retrying command fetch\n"); + dev_err(dev, "retrying command fetch\n"); return; case CMDQ_ERR_CERROR_NONE_IDX: return; @@ -424,9 +423,12 @@ static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, * not to touch any of the shadow cmdq state. */ queue_read(cmd, Q_ENT(q, cons), q->ent_dwords); - dev_err(smmu->dev, "skipping command in error state:\n"); + dev_err(dev, "skipping command in error state:\n"); for (i = 0; i < ARRAY_SIZE(cmd); ++i) - dev_err(smmu->dev, "\t0x%016llx\n", (unsigned long long)cmd[i]); + dev_err(dev, "\t0x%016llx\n", (unsigned long long)cmd[i]); + + if (q->quirks & CMDQ_QUIRK_SYNC_CS_NONE_ONLY) + cmd_sync.sync.cs_none = true; /* Convert the erroneous command into a CMD_SYNC */ arm_smmu_cmdq_build_cmd(cmd, &cmd_sync); @@ -436,7 +438,7 @@ static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, static void arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu) { - __arm_smmu_cmdq_skip_err(smmu, &smmu->cmdq.q); + __arm_smmu_cmdq_skip_err(smmu->dev, &smmu->cmdq.q); } /* diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 4af0976a2338..3046c1028e66 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -760,6 +760,7 @@ int arm_smmu_atc_inv_domain(struct arm_smmu_domain *smmu_domain, int ssid, int arm_smmu_cmdq_init(struct arm_smmu_device *smmu, struct arm_smmu_cmdq *cmdq); +void __arm_smmu_cmdq_skip_err(struct device *dev, struct arm_smmu_queue *q); #ifdef CONFIG_ARM_SMMU_V3_SVA bool arm_smmu_sva_supported(struct arm_smmu_device *smmu);