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Received: from kirsty.vergenet.net ([202.4.237.240]) by casper.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gRGbW-0005w7-R4 for linux-arm-kernel@lists.infradead.org; Mon, 26 Nov 2018 13:07:14 +0000 Received: from reginn.horms.nl (watermunt.horms.nl [80.127.179.77]) by kirsty.vergenet.net (Postfix) with ESMTPA id CD3C925BF65; Mon, 26 Nov 2018 23:55:16 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=verge.net.au; s=mail; t=1543236917; bh=AooTNqe7ihAhleqi8A8RRWNLWac9NykgVhuFhB+T9jU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=rciieLaFj4ko90D69lbPjLDycX5rTztH7Z4k86GR4E0Yo/ZWBFsX1KU8txWVWLd5e VZp+WNcBypRi4vLT6UwTByupuanTQpQfOOycd12Y8j2SPK2OlwW9x7rF+QcPkqwH53 JuvfxNVOWo0TWwYFraGcCkDB63SVB0Vju7N+fKi0= Received: by reginn.horms.nl (Postfix, from userid 7100) id C3295940AF0; Mon, 26 Nov 2018 13:55:09 +0100 (CET) From: Simon Horman To: linux-renesas-soc@vger.kernel.org Subject: [PATCH 32/40] arm64: dts: renesas: r8a77990: ebisu: Add and enable PCIe device node Date: Mon, 26 Nov 2018 13:54:58 +0100 Message-Id: X-Mailer: git-send-email 2.11.0 In-Reply-To: References: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181126_130711_152531_648C2826 X-CRM114-Status: GOOD ( 12.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Simon Horman , Takeshi Kihara , Magnus Damm , linux-arm-kernel@lists.infradead.org, Marek Vasut MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Takeshi Kihara This patch adds PCI express channel 0 device node to the R8A77990 SoC and enables PCIEC0 PCI express controller on the Ebisu board. Signed-off-by: Takeshi Kihara Signed-off-by: Marek Vasut Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 8 ++++++ arch/arm64/boot/dts/renesas/r8a77990.dtsi | 34 ++++++++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts index 2f1cbcde8ae0..3e4d90b654cc 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts +++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts @@ -444,6 +444,14 @@ status = "okay"; }; +&pcie_bus_clk { + clock-frequency = <100000000>; +}; + +&pciec0 { + status = "okay"; +}; + &pfc { avb_pins: avb { mux { diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index a2524fc138a2..46868dacbeef 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -85,6 +85,13 @@ clock-frequency = <0>; }; + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + pmu_a53 { compatible = "arm,cortex-a53-pmu"; interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, @@ -1610,6 +1617,33 @@ }; }; + pciec0: pcie@fe000000 { + compatible = "renesas,pcie-r8a77990", + "renesas,pcie-rcar-gen3"; + reg = <0 0xfe000000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 + 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 + 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 + 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; + interrupts = , + , + ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 319>; + status = "disabled"; + }; + prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>;