From patchwork Thu Feb 17 14:24:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robin Murphy X-Patchwork-Id: 12750277 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E6BE1C433F5 for ; Thu, 17 Feb 2022 14:34:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=6cUAorYrd9dcg7rk+HxIMHoGWwS8+DtvSmTdJAFNUGE=; b=SvaXFAklelHSTt 3y4JLoW6SsWn+SY2wHTvfYuwPInUh70dCn8NJ27LfyIJU06D5xkmQL7dEvN9zuYlPq0TDNhveBr+Z n7LvJX+5/HeriznmogiBY0uuPmt/oAZw9mMVq0QGfFLvkrIIJRnvqlBCWf8YlQUR6Tdpg/2A//9IS iX4L1RcS9Z0c8qpyH1h5KD+XK/9agSpALgr02OWVEF0lkzlCRRsoEhVa2sUC/cuqETa75hu9edoTc BQE1k38FPnW/VkGgAyxIMu3CWZ0Sglu2cIzpOUKvubzGrtBI3A7tqbvFaduUXGoMuQpuTCsVwV1sn 2OwIcX6Ygboi6/sXxhbg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nKhqY-00B2no-GY; Thu, 17 Feb 2022 14:33:26 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nKhhx-00AzSW-1z for linux-arm-kernel@lists.infradead.org; Thu, 17 Feb 2022 14:24:34 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6BB481474; Thu, 17 Feb 2022 06:24:32 -0800 (PST) Received: from e121345-lin.cambridge.arm.com (e121345-lin.cambridge.arm.com [10.1.196.40]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 482423F718; Thu, 17 Feb 2022 06:24:31 -0800 (PST) From: Robin Murphy To: will@kernel.org, mark.rutland@arm.com Cc: lorenzo.pieralisi@arm.com, sudeep.holla@arm.com, linux-arm-kernel@lists.infradead.org, jean-philippe@linaro.org, leo.yan@linaro.org, noda.akio@socionext.com Subject: [PATCH 3/6] iommu/arm-smmu: Add DT PMU support Date: Thu, 17 Feb 2022 14:24:17 +0000 Message-Id: X-Mailer: git-send-email 2.28.0.dirty In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220217_062433_252573_BC5C72A7 X-CRM114-Status: GOOD ( 15.12 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Since IORT describes PMU interrupts rather inflexibly as an inherent part of the SMMU, the best way to avoid excessive complexity is to make the way we handle DT look as similar as possible. Fortunately the de-facto standard for mentioning PMU interrupts at all under the current binding has been to include them in the global interrupt count, listing them after the actual fault interrupt(s), so we can capitalise on that. It's about 9 years too late to redefine "#global-interrupts" to exclude anything other than context interrupts without breaking compatibility, so we're stuck with a slightly convoluted definition of PMU interrupts as an optional subdivision of the "global" interrupts, but it works. Signed-off-by: Robin Murphy --- Not sure whether the count-backwards-from-the-middle nature of "number of PMU interrupts" is too ugly and "index of first PMU interrupt" might be any better. --- .../devicetree/bindings/iommu/arm,smmu.yaml | 19 ++++++++++++++++++- drivers/iommu/arm/arm-smmu/arm-smmu.c | 4 ++++ 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index da5381c8ee11..9d39df42528a 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -87,10 +87,18 @@ properties: '#global-interrupts': description: The number of global interrupts exposed by the device. + Includes the count of PMU interrupts, if present. $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 260 # 2 secure, 2 non-secure, and up to 256 perf counters + '#pmu-interrupts': + description: The number of PMU interrupts. Must be equal to the number of + implemented counter groups. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 256 + '#iommu-cells': enum: [ 1, 2 ] description: | @@ -115,6 +123,10 @@ properties: context bank. In the case of a single, combined interrupt, it must be listed multiple times. + If a PMU is present, the global interrupt entries consist of any fault + interrupts first, followed by #pmu-interrupts entries, one per implemented + counter group, specified in order of their indexing by the SMMU. + dma-coherent: description: | Present if page table walks made by the SMMU are cache coherent with the @@ -190,9 +202,14 @@ examples: smmu1: iommu@ba5e0000 { compatible = "arm,smmu-v1"; reg = <0xba5e0000 0x10000>; - #global-interrupts = <2>; + #global-interrupts = <6>; /* 2 fault + 4 PMU */ + #pmu-interrupts = <4>; interrupts = <0 32 4>, <0 33 4>, + <0 94 4>, /* This is the first PMU interrupt */ + <0 95 4>, + <0 96 4>, + <0 97 4>, <0 34 4>, /* This is the first context interrupt */ <0 35 4>, <0 36 4>, diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index cbfe4cc914f0..8d6c8106fc1d 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -1995,6 +1995,10 @@ static int arm_smmu_device_dt_probe(struct arm_smmu_device *smmu, return dev_err_probe(dev, -ENODEV, "missing #global-interrupts property\n"); *pmu_irqs = 0; + of_property_read_u32(dev->of_node, "#pmu-interrupts", pmu_irqs); + if (*pmu_irqs > *global_irqs) + return dev_err_probe(dev, -EINVAL, "invalid #pmu_interrupts property"); + *global_irqs -= *pmu_irqs; data = of_device_get_match_data(dev); smmu->version = data->version;