From patchwork Tue Jun 18 15:20:36 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 2744251 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 3227E9F8E1 for ; Tue, 18 Jun 2013 17:06:28 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DF91420186 for ; Tue, 18 Jun 2013 17:06:26 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 60D7020157 for ; Tue, 18 Jun 2013 17:06:25 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Uoxna-0004Jo-UF; Tue, 18 Jun 2013 15:26:29 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Uoxkw-0003OU-Fa; Tue, 18 Jun 2013 15:23:38 +0000 Received: from mail-pa0-x22e.google.com ([2607:f8b0:400e:c03::22e]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Uoxk1-0003HX-T8 for linux-arm-kernel@lists.infradead.org; Tue, 18 Jun 2013 15:22:43 +0000 Received: by mail-pa0-f46.google.com with SMTP id fa11so4118302pad.19 for ; Tue, 18 Jun 2013 08:22:20 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :in-reply-to:references:x-gm-message-state; bh=xU8UpjtXPVz3nxoflPfeBcdU36rGOf1iqWAK0xidKeU=; b=bnLN/AtELTA1AXcUXUiwkhreQ86uHWFWrEFzecEvmrMWGZ68rA4hGdCOYIIf2r39CD xX2twh5Vqsa9pN4NdYowAUC6aqqMIW/tgHfQTTe4qsfZRDsVmzjh8kwC93GoSV/aCUt7 1UwvhecSqxy+lmroq1sNnpWgzRj+hk52c2SAOSVltXPOhRaZ4v/Yk4//DvvHk3LCfht1 fY/4za0Z3xNhDXkBoNCfich6WDsgyU0m4hdUvX/ssb0CVHR+y6e/7krrlhq43n1RzB4R WfB1n79VfO0aVfQ4PvD7Vz7oH32kDZ9+LTq1tV6qMersBTLLOz5/eDISWRGrEbBgbEVG /rdA== X-Received: by 10.68.107.225 with SMTP id hf1mr17493055pbb.130.1371568940365; Tue, 18 Jun 2013 08:22:20 -0700 (PDT) Received: from localhost ([122.167.240.191]) by mx.google.com with ESMTPSA id xz1sm20127071pab.5.2013.06.18.08.22.17 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 18 Jun 2013 08:22:19 -0700 (PDT) From: Viresh Kumar To: wim@iguana.be Subject: [PATCH V3 12/14] watchdog/mpcore_wdt: use correct clk_rate to program timeout Date: Tue, 18 Jun 2013 20:50:36 +0530 Message-Id: X-Mailer: git-send-email 1.7.12.rc2.18.g61b472e In-Reply-To: References: In-Reply-To: References: X-Gm-Message-State: ALoCoQkfXcvFtU/JtjTbDlMGlXArDtVwWV6kc4BcuJd0QAMEl2Bd87YA3/71mcQE7ReKHf/cYI5N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130618_112242_128605_301CD0C4 X-CRM114-Status: GOOD ( 19.13 ) X-Spam-Score: -1.9 (-) Cc: marc.zyngier@arm.com, Viresh Kumar , linux-watchdog@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Currently, mpcore wdt driver doesn't use exact clk_rate to program timeout in hardware. This patch provides two ways of doing so: - either use clk_get_rate() if clk_get passes - use clk_rate passed via module param Signed-off-by: Viresh Kumar --- arch/arm/include/asm/smp_twd.h | 10 +++++ drivers/watchdog/mpcore_wdt.c | 99 ++++++++++++++++++++++++++++++++++-------- 2 files changed, 90 insertions(+), 19 deletions(-) diff --git a/arch/arm/include/asm/smp_twd.h b/arch/arm/include/asm/smp_twd.h index a62bcfa..a9791c5 100644 --- a/arch/arm/include/asm/smp_twd.h +++ b/arch/arm/include/asm/smp_twd.h @@ -13,11 +13,21 @@ #define TWD_WDOG_RESETSTAT 0x30 #define TWD_WDOG_DISABLE 0x34 +#define TWD_WDOG_LOAD_MIN 0x00000000 +#define TWD_WDOG_LOAD_MAX 0xFFFFFFFF + #define TWD_TIMER_CONTROL_ENABLE (1 << 0) #define TWD_TIMER_CONTROL_ONESHOT (0 << 1) #define TWD_TIMER_CONTROL_PERIODIC (1 << 1) #define TWD_TIMER_CONTROL_IT_ENABLE (1 << 2) +#define TWD_WDOG_CONTROL_ENABLE (1 << 0) +#define TWD_WDOG_CONTROL_IRQ_ENABLE (1 << 2) +#define TWD_WDOG_CONTROL_WDT_MODE (1 << 3) +#define TWD_WDOG_CONTROL_WDT_PRESCALE(x) ((x) << 8) +#define TWD_WDOG_CONTROL_PRESCALE_MIN 0x00 +#define TWD_WDOG_CONTROL_PRESCALE_MAX 0xFF + #define TWD_WDOG_RESETSTAT_MASK 0x1 #include diff --git a/drivers/watchdog/mpcore_wdt.c b/drivers/watchdog/mpcore_wdt.c index 1a1a1fd..64878a7 100644 --- a/drivers/watchdog/mpcore_wdt.c +++ b/drivers/watchdog/mpcore_wdt.c @@ -42,7 +42,10 @@ struct mpcore_wdt { void __iomem *base; spinlock_t lock; struct clk *clk; + unsigned long clk_rate; /* In Hz */ int irq; + unsigned int prescale; + unsigned int load_val; unsigned int perturb; }; @@ -61,6 +64,11 @@ MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); +static int clk_rate; +module_param(clk_rate, int, 0); +MODULE_PARM_DESC(clk_rate, + "Watchdog clock rate in Hz, required if clk_get() fails"); + #define ONLY_TESTING 0 static int mpcore_noboot = ONLY_TESTING; module_param(mpcore_noboot, int, 0); @@ -96,17 +104,10 @@ static irqreturn_t mpcore_wdt_fire(int irq, void *arg) static int mpcore_wdt_ping(struct watchdog_device *wdd) { struct mpcore_wdt *wdt = watchdog_get_drvdata(wdd); - unsigned long count; spin_lock(&wdt->lock); - /* Assume prescale is set to 256 */ - count = readl_relaxed(wdt->base + TWD_WDOG_COUNTER); - count = (0xFFFFFFFFU - count) * (HZ / 5); - count = (count / 256) * mpcore_margin; - - /* Reload the counter */ - writel_relaxed(count + wdt->perturb, wdt->base + TWD_WDOG_LOAD); - wdt->perturb = wdt->perturb ? 0 : 1; + writel_relaxed(wdt->load_val + wdt->perturb, wdt->base + TWD_WDOG_LOAD); + wdt->perturb = !wdt->perturb; spin_unlock(&wdt->lock); return 0; @@ -136,6 +137,7 @@ static int mpcore_wdt_stop(struct watchdog_device *wdd) static int mpcore_wdt_start(struct watchdog_device *wdd) { struct mpcore_wdt *wdt = watchdog_get_drvdata(wdd); + u32 val, mode; int ret; dev_info(wdt->dev, "enabling watchdog\n"); @@ -151,20 +153,70 @@ static int mpcore_wdt_start(struct watchdog_device *wdd) /* This loads the count register but does NOT start the count yet */ mpcore_wdt_ping(wdd); - if (mpcore_noboot) { - /* Enable watchdog - prescale=256, watchdog mode=0, enable=1 */ - writel_relaxed(0x0000FF01, wdt->base + TWD_WDOG_CONTROL); - } else { - /* Enable watchdog - prescale=256, watchdog mode=1, enable=1 */ - writel_relaxed(0x0000FF09, wdt->base + TWD_WDOG_CONTROL); - } + if (mpcore_noboot) + mode = 0; + else + mode = TWD_WDOG_CONTROL_WDT_MODE; + + spin_lock(&wdt->lock); + + val = TWD_WDOG_CONTROL_WDT_PRESCALE(wdt->prescale) | + TWD_WDOG_CONTROL_ENABLE | mode; + writel_relaxed(val, wdt->base + TWD_WDOG_CONTROL); + + spin_unlock(&wdt->lock); return 0; } -static int mpcore_wdt_set_heartbeat(struct watchdog_device *wdd, unsigned int t) +/* binary search */ +static inline void bsearch(u32 *var, u32 var_start, u32 var_end, + const u64 param, const u32 timeout, u32 rate) { - mpcore_margin = t; + u64 tmp = 0; + + /* get the lowest var value that can satisfy our requirement */ + while (var_start < var_end) { + tmp = var_start; + tmp += var_end; + tmp = div_u64(tmp, 2); + if (timeout > div_u64((param + 1) * (tmp + 1), rate)) { + if (var_start == tmp) + break; + else + var_start = tmp; + } else { + if (var_end == tmp) + break; + else + var_end = tmp; + } + } + *var = tmp; +} + +static int +mpcore_wdt_set_heartbeat(struct watchdog_device *wdd, unsigned int timeout) +{ + struct mpcore_wdt *wdt = watchdog_get_drvdata(wdd); + unsigned int psc, rate = wdt->clk_rate; + u64 load = 0; + + /* get appropriate value of psc and load */ + bsearch(&psc, TWD_WDOG_CONTROL_PRESCALE_MIN, + TWD_WDOG_CONTROL_PRESCALE_MAX, TWD_WDOG_LOAD_MAX, + timeout, rate); + bsearch((u32 *)&load, TWD_WDOG_LOAD_MIN, TWD_WDOG_LOAD_MAX, psc, + timeout, rate); + + spin_lock(&wdt->lock); + wdt->prescale = psc; + wdt->load_val = load; + + /* roundup timeout to closest positive integer value */ + mpcore_margin = div_u64((psc + 1) * (load + 1) + (rate / 2), rate); + spin_unlock(&wdt->lock); + return 0; } @@ -240,7 +292,10 @@ static int mpcore_wdt_probe(struct platform_device *pdev) wdt->clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(wdt->clk)) { dev_warn(&pdev->dev, "Clock not found\n"); + wdt->clk_rate = clk_rate; } else { + wdt->clk_rate = clk_get_rate(wdt->clk); + ret = clk_prepare_enable(wdt->clk); if (ret) { dev_err(wdt->dev, "clock prepare-enable failed"); @@ -253,6 +308,12 @@ static int mpcore_wdt_probe(struct platform_device *pdev) mpcore_wdt_stop(&wdt->wdd); + if (!wdt->clk_rate) { + dev_err(&pdev->dev, "Clock rate can't be zero\n"); + ret = -EINVAL; + goto err_put_clk; + } + ret = watchdog_register_device(&wdt->wdd); if (ret) { dev_err(wdt->dev, "watchdog_register_device() failed: %d\n", @@ -270,7 +331,7 @@ static int mpcore_wdt_probe(struct platform_device *pdev) TIMER_MARGIN); } - mpcore_wdt_set_heartbeat(NULL, mpcore_margin); + mpcore_wdt_set_heartbeat(&wdt->wdd, mpcore_margin); dev_info(wdt->dev, "MPcore Watchdog Timer: 0.1. mpcore_noboot=%d " "mpcore_margin=%d sec (nowayout= %d)\n", mpcore_noboot, mpcore_margin, nowayout);