From patchwork Thu Feb 1 14:19:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 13541177 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1F5D2C4828D for ; Thu, 1 Feb 2024 14:19:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=CfwgCbI1w5Nmqbu47Zc7vvYaAB/NaBz7VTu3ivsO+ak=; b=LxdHgeCPYK/BPg xDqlN0UL+j6a9YHysIW1ViLFk75L+x5RCmRcHrb6W5mV8RZ+HzHd3AT8FGibQUsBkHB4CilE4TECS byAYJPGwGnfWgKCg4Y2sB8/CLJI7FUPCGo0PVrA7c/8vEu9nxc1tTtB13ADYYI6rGgLN6cbvDNRk8 rzhyCmn8Q553sB8vB+muoLR55Lr4/YZb0myx14keUlZeBnsmAW6AyoroQhetRO/flsKd6jsa3F4xw h9Jhl5mAbXC9lNBYFaQIQCRFCpIiHrkjt09rV8rPDIoyQC2reeQozqkTySMhhoXx0WZdxTPlyL/9K zF3XExd8d03iDrYkgN5Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rVXud-00000008FzI-1zLn; Thu, 01 Feb 2024 14:19:31 +0000 Received: from xavier.telenet-ops.be ([2a02:1800:120:4::f00:14]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rVXuY-00000008Fui-2WUV for linux-arm-kernel@lists.infradead.org; Thu, 01 Feb 2024 14:19:29 +0000 Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed40:88f0:c83b:bafa:cdc3]) by xavier.telenet-ops.be with bizsmtp id hqKM2B0084efzLr01qKMiE; Thu, 01 Feb 2024 15:19:21 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.95) (envelope-from ) id 1rVXtc-00Gv4l-5P; Thu, 01 Feb 2024 15:19:21 +0100 Received: from geert by rox.of.borg with local (Exim 4.95) (envelope-from ) id 1rVXuT-00AXdV-4V; Thu, 01 Feb 2024 15:19:21 +0100 From: Geert Uytterhoeven To: linux-renesas-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Duy Nguyen , Geert Uytterhoeven Subject: [PATCH 4/5] arm64: dts: renesas: r8a779h0: Add CPU core clocks Date: Thu, 1 Feb 2024 15:19:19 +0100 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240201_061926_887489_1F15F308 X-CRM114-Status: UNSURE ( 8.55 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Duy Nguyen Describe the clocks for the four Cortex-A76 CPU cores. CA76 CPU cores 0,1,2,3 are clocked by ZC0,ZC1,ZC2,ZC3. Signed-off-by: Duy Nguyen Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index b3255bba69e3e6da..622775f6160f55bd 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -43,6 +43,7 @@ a76_0: cpu@0 { next-level-cache = <&L3_CA76>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC0>; }; a76_1: cpu@100 { @@ -53,6 +54,7 @@ a76_1: cpu@100 { next-level-cache = <&L3_CA76>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC1>; }; a76_2: cpu@200 { @@ -63,6 +65,7 @@ a76_2: cpu@200 { next-level-cache = <&L3_CA76>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC2>; }; a76_3: cpu@300 { @@ -73,6 +76,7 @@ a76_3: cpu@300 { next-level-cache = <&L3_CA76>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC3>; }; idle-states {