@@ -2406,6 +2406,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
struct arm_smmu_device *smmu;
struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
struct arm_smmu_master *master;
+ bool byapss_ste, skip_cdtab;
if (!fwspec)
return -ENOENT;
@@ -2441,6 +2442,24 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
master->domain = smmu_domain;
+ /*
+ * When master attaches ARM_SMMU_DOMAIN_BYPASS to its single substream,
+ * set STE.Config to "bypass" and skip a CD table allocation. Otherwise,
+ * set STE.Config to "stage-1 translate" and allocate a CD table for its
+ * multiple stage-1 substream support, unless with a stage-2 domain in
+ * which case set STE.config to "stage-2 translate" and skip a CD table.
+ */
+ if (smmu_domain->stage == ARM_SMMU_DOMAIN_BYPASS && !master->ssid_bits) {
+ byapss_ste = true;
+ skip_cdtab = true;
+ } else {
+ byapss_ste = false;
+ if (smmu_domain->stage == ARM_SMMU_DOMAIN_S2)
+ skip_cdtab = true;
+ else
+ skip_cdtab = false;
+ }
+
/*
* The SMMU does not support enabling ATS with bypass. When the STE is
* in bypass (STE.Config[2:0] == 0b100), ATS Translation Requests and
@@ -2448,22 +2467,22 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
* stream (STE.EATS == 0b00), causing F_BAD_ATS_TREQ and
* F_TRANSL_FORBIDDEN events (IHI0070Ea 5.2 Stream Table Entry).
*/
- if (smmu_domain->stage != ARM_SMMU_DOMAIN_BYPASS)
+ if (!byapss_ste)
master->ats_enabled = arm_smmu_ats_supported(master);
spin_lock_irqsave(&smmu_domain->devices_lock, flags);
list_add(&master->domain_head, &smmu_domain->devices);
spin_unlock_irqrestore(&smmu_domain->devices_lock, flags);
- if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) {
- if (!master->cd_table.cdtab) {
- ret = arm_smmu_alloc_cd_tables(master);
- if (ret) {
- master->domain = NULL;
- goto out_list_del;
- }
+ if (!skip_cdtab && !master->cd_table.cdtab) {
+ ret = arm_smmu_alloc_cd_tables(master);
+ if (ret) {
+ master->domain = NULL;
+ goto out_list_del;
}
+ }
+ if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) {
/*
* Prevent SVA from concurrently modifying the CD or writing to
* the CD entry
If a master has only a default substream, it can skip CD/translation table allocations when being attached to an IDENTITY domain, by simply setting STE to the "bypass" mode (STE.Config[2:0] == 0b100). If a master has multiple substreams, it will still need a CD table for the non-default substreams when being attached to an IDENTITY domain, in which case the STE.Config is set to the "stage-1 translate" mode while STE.S1DSS field instead is set to the "bypass" mode (STE.S1DSS[1:0] == 0b01). If a master is attached to a stage-2 domain, it does not need a CD table, while the STE.Config is set to the "stage-2 translate" mode. Add boolean bypass_ste and skip_cdtab flags in arm_smmu_attach_dev(), to handle clearly the cases above, which also corrects the conditions at the ats_enabled setting and arm_smmu_alloc_cd_tables() callback to cover the second use case. Signed-off-by: Nicolin Chen <nicolinc@nvidia.com> --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 35 ++++++++++++++++----- 1 file changed, 27 insertions(+), 8 deletions(-)