From patchwork Mon Nov 14 12:49:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 13042284 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A59C5C4332F for ; Mon, 14 Nov 2022 12:51:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=sXDYwWIb70t45jpyvFkntCvDo8gTuBVksGMMzSKS7fE=; b=W9trCgj17Xe5wY g2bM9VhCy4v7FFr2MxHpvjfT/Ch/9lT/9KoG0jDI2QzY0Z1Aujt7oVsmoEyr03pnFclwcxsv0hP7h iZuHgwrnwfylE6r4RnNhiKjguuBVAO4iIF3kbbIdQDeBh6DzdsPL1DhbHVkjHGiuDrMTCQxMlrnJ0 Z+q/8mXFWn7IntP5xgY5UxZimlGxvsjYyhasOf7WHPRBwm0qTxBL/0myBDFsmsysE6nwvUU4E3iGi ESMejuHD5+dTWOEean52Vtwaf15Z//kT/Nrp9g1iiDRbhHenj4QeQrEBC48yCuVVmmfdOjF72Trne wGtXBdSZ1EtbKY8xO0OQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ouYv1-000vsX-LS; Mon, 14 Nov 2022 12:50:31 +0000 Received: from albert.telenet-ops.be ([2a02:1800:110:4::f00:1a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ouYto-000vEQ-8K for linux-arm-kernel@lists.infradead.org; Mon, 14 Nov 2022 12:49:20 +0000 Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed10:9cda:b28b:1ded:8138]) by albert.telenet-ops.be with bizsmtp id kCp6280063NlhLw06Cp6XX; Mon, 14 Nov 2022 13:49:09 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1ouYtd-000UUB-MN; Mon, 14 Nov 2022 13:49:05 +0100 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1ouYtd-003gz6-0p; Mon, 14 Nov 2022 13:49:05 +0100 From: Geert Uytterhoeven To: Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Geert Uytterhoeven Subject: [PATCH 2/5] arm64: dts: renesas: r8a779g0: Add secondary CA76 CPU cores Date: Mon, 14 Nov 2022 13:49:01 +0100 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221114_044916_512653_131A3FB3 X-CRM114-Status: GOOD ( 12.10 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Complete the description of the Cortex-A76 CPU cores and L3 cache controllers on the Renesas R-Car V4H (R8A779G0) SoC, including CPU topology and PSCI support for enabling CPU cores. R-Car V4H has 4 Cortex-A76 cores, grouped in 2 clusters. Based on a patch in the BSP by Takeshi Kihara. Signed-off-by: Geert Uytterhoeven --- Changes compared to the BSP: - Move device_type and enable-method properties, - Fix PSCI compatible value for PSCI v1.0, - Drop "arm,armv8" compatible values. --- arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 70 +++++++++++++++++++++-- 1 file changed, 65 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index ef75e2603f5ac9d9..dc5f27c114a7ad96 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -18,12 +18,60 @@ cpus { #address-cells = <1>; #size-cells = <0>; + cpu-map { + cluster0 { + core0 { + cpu = <&a76_0>; + }; + core1 { + cpu = <&a76_1>; + }; + }; + + cluster1 { + core0 { + cpu = <&a76_2>; + }; + core1 { + cpu = <&a76_3>; + }; + }; + }; + a76_0: cpu@0 { compatible = "arm,cortex-a76"; reg = <0>; device_type = "cpu"; power-domains = <&sysc R8A779G0_PD_A1E0D0C0>; next-level-cache = <&L3_CA76_0>; + enable-method = "psci"; + }; + + a76_1: cpu@100 { + compatible = "arm,cortex-a76"; + reg = <0x100>; + device_type = "cpu"; + power-domains = <&sysc R8A779G0_PD_A1E0D0C1>; + next-level-cache = <&L3_CA76_0>; + enable-method = "psci"; + }; + + a76_2: cpu@10000 { + compatible = "arm,cortex-a76"; + reg = <0x10000>; + device_type = "cpu"; + power-domains = <&sysc R8A779G0_PD_A1E0D1C0>; + next-level-cache = <&L3_CA76_1>; + enable-method = "psci"; + }; + + a76_3: cpu@10100 { + compatible = "arm,cortex-a76"; + reg = <0x10100>; + device_type = "cpu"; + power-domains = <&sysc R8A779G0_PD_A1E0D1C1>; + next-level-cache = <&L3_CA76_1>; + enable-method = "psci"; }; L3_CA76_0: cache-controller-0 { @@ -32,6 +80,18 @@ L3_CA76_0: cache-controller-0 { cache-unified; cache-level = <3>; }; + + L3_CA76_1: cache-controller-1 { + compatible = "cache"; + power-domains = <&sysc R8A779G0_PD_A2E0D1>; + cache-unified; + cache-level = <3>; + }; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; }; extal_clk: extal { @@ -1088,7 +1148,7 @@ gic: interrupt-controller@f1000000 { reg = <0x0 0xf1000000 0 0x20000>, <0x0 0xf1060000 0 0x110000>; interrupts = ; + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; prr: chipid@fff00044 { @@ -1099,9 +1159,9 @@ prr: chipid@fff00044 { timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; };