Message ID | cd26a3bdc9f29e237089395fbba93e28549ddf25.1519874655.git.sean.wang@mediatek.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
On Thu, Mar 01, 2018 at 11:27:50AM +0800, sean.wang@mediatek.com wrote: > From: Sean Wang <sean.wang@mediatek.com> > > Just add binding for a fixed-factor clock axisel_d4, which would be > referenced by PWM devices on MT7623 or MT2701 SoC. > > Cc: stable@vger.kernel.org > Fixes: 1de9b21633d6 ("clk: mediatek: Add dt-bindings for MT2701 clocks") > Signed-off-by: Sean Wang <sean.wang@mediatek.com> > Cc: Rob Herring <robh+dt@kernel.org> > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: devicetree@vger.kernel.org > --- > include/dt-bindings/clock/mt2701-clk.h | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) Reviewed-by: Rob Herring <robh@kernel.org>
Quoting sean.wang@mediatek.com (2018-02-28 19:27:50) > From: Sean Wang <sean.wang@mediatek.com> > > Just add binding for a fixed-factor clock axisel_d4, which would be > referenced by PWM devices on MT7623 or MT2701 SoC. > > Cc: stable@vger.kernel.org > Fixes: 1de9b21633d6 ("clk: mediatek: Add dt-bindings for MT2701 clocks") > Signed-off-by: Sean Wang <sean.wang@mediatek.com> > Cc: Rob Herring <robh+dt@kernel.org> > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: devicetree@vger.kernel.org > --- Applied to clk-next
diff --git a/include/dt-bindings/clock/mt2701-clk.h b/include/dt-bindings/clock/mt2701-clk.h index 551f760..24e93df 100644 --- a/include/dt-bindings/clock/mt2701-clk.h +++ b/include/dt-bindings/clock/mt2701-clk.h @@ -176,7 +176,8 @@ #define CLK_TOP_AUD_EXT1 156 #define CLK_TOP_AUD_EXT2 157 #define CLK_TOP_NFI1X_PAD 158 -#define CLK_TOP_NR 159 +#define CLK_TOP_AXISEL_D4 159 +#define CLK_TOP_NR 160 /* APMIXEDSYS */