| Message ID | cf265add1502a75c4d6e6261ab1570c665e82c83.1565088423.git.leonard.crestez@nxp.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | interconnect: Add imx support via devfreq | expand |
On 06.08.19 12:55, Leonard Crestez wrote: > This adds a platform driver for the i.MX8MM SoC. > > Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> > Signed-off-by: Alexandre Bailon <abailon@baylibre.com> > --- > drivers/interconnect/imx/Kconfig | 4 + > drivers/interconnect/imx/Makefile | 1 + > drivers/interconnect/imx/imx8mm.c | 114 ++++++++++++++++++++++ > include/dt-bindings/interconnect/imx8mm.h | 49 ++++++++++ > 4 files changed, 168 insertions(+) > create mode 100644 drivers/interconnect/imx/imx8mm.c > create mode 100644 include/dt-bindings/interconnect/imx8mm.h > Hi Leonard, Do you plan to add such a driver for imx8mq too? And I guess the commit message could be more descriptive here. thanks for your work, martin
On 21.08.2019 17:03, Martin Kepplinger wrote: > On 06.08.19 12:55, Leonard Crestez wrote: >> This adds a platform driver for the i.MX8MM SoC. >> >> Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> >> Signed-off-by: Alexandre Bailon <abailon@baylibre.com> >> --- >> drivers/interconnect/imx/Kconfig | 4 + >> drivers/interconnect/imx/Makefile | 1 + >> drivers/interconnect/imx/imx8mm.c | 114 ++++++++++++++++++++++ >> include/dt-bindings/interconnect/imx8mm.h | 49 ++++++++++ >> 4 files changed, 168 insertions(+) >> create mode 100644 drivers/interconnect/imx/imx8mm.c >> create mode 100644 include/dt-bindings/interconnect/imx8mm.h > > Do you plan to add such a driver for imx8mq too? Yes! The topology is different (serving different IP blocks) but no functional code changes are required between 8mm 8mn 8mq. I already wrote the code and tested it but didn't post because I want to get the core parts in first. I periodically push my "full" work-in-progress to github: https://github.com/cdleonard/linux/commits/next_imx8mm_busfreq You need out-of-tree ATF changes or devfreq probe will fail: https://github.com/cdleonard/arm-trusted-firmware/commits/imx_2.0.y_busfreq -- Regards, Leonard
On 21.08.19 16:21, Leonard Crestez wrote: > On 21.08.2019 17:03, Martin Kepplinger wrote: >> On 06.08.19 12:55, Leonard Crestez wrote: >>> This adds a platform driver for the i.MX8MM SoC. >>> >>> Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> >>> Signed-off-by: Alexandre Bailon <abailon@baylibre.com> >>> --- >>> drivers/interconnect/imx/Kconfig | 4 + >>> drivers/interconnect/imx/Makefile | 1 + >>> drivers/interconnect/imx/imx8mm.c | 114 ++++++++++++++++++++++ >>> include/dt-bindings/interconnect/imx8mm.h | 49 ++++++++++ >>> 4 files changed, 168 insertions(+) >>> create mode 100644 drivers/interconnect/imx/imx8mm.c >>> create mode 100644 include/dt-bindings/interconnect/imx8mm.h >> >> Do you plan to add such a driver for imx8mq too? > > Yes! The topology is different (serving different IP blocks) but no > functional code changes are required between 8mm 8mn 8mq. > > I already wrote the code and tested it but didn't post because I want to > get the core parts in first. I periodically push my "full" > work-in-progress to github: > > https://github.com/cdleonard/linux/commits/next_imx8mm_busfreq > > You need out-of-tree ATF changes or devfreq probe will fail: > > https://github.com/cdleonard/arm-trusted-firmware/commits/imx_2.0.y_busfreq > Thanks for the update, that's good to hear. I'll get back to you when I come around to test this and wish you good progress until then :) martin
Hi Leonard, On 2019-08-21 07:26, Martin Kepplinger wrote: > On 21.08.19 16:21, Leonard Crestez wrote: >> On 21.08.2019 17:03, Martin Kepplinger wrote: >>> On 06.08.19 12:55, Leonard Crestez wrote: >>>> This adds a platform driver for the i.MX8MM SoC. >>>> >>>> Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> >>>> Signed-off-by: Alexandre Bailon <abailon@baylibre.com> >>>> --- >>>> drivers/interconnect/imx/Kconfig | 4 + >>>> drivers/interconnect/imx/Makefile | 1 + >>>> drivers/interconnect/imx/imx8mm.c | 114 >>>> ++++++++++++++++++++++ >>>> include/dt-bindings/interconnect/imx8mm.h | 49 ++++++++++ >>>> 4 files changed, 168 insertions(+) >>>> create mode 100644 drivers/interconnect/imx/imx8mm.c >>>> create mode 100644 include/dt-bindings/interconnect/imx8mm.h >>> >>> Do you plan to add such a driver for imx8mq too? >> >> Yes! The topology is different (serving different IP blocks) but no >> functional code changes are required between 8mm 8mn 8mq. >> >> I already wrote the code and tested it but didn't post because I want >> to >> get the core parts in first. I periodically push my "full" >> work-in-progress to github: >> >> https://github.com/cdleonard/linux/commits/next_imx8mm_busfreq >> >> You need out-of-tree ATF changes or devfreq probe will fail: >> >> https://github.com/cdleonard/arm-trusted-firmware/commits/imx_2.0.y_busfreq >> > > Thanks for the update, that's good to hear. I'll get back to you when I > come around to test this and wish you good progress until then :) > I've taken up this work while Martin is on leave. I've integrated your u-boot and ATF on our board and I have a couple of questions. Our board is running imx8mq B0 (Rev 2.0) silicon. It looks like this line limits the training frequencies to 800 MHz and 166 MHz https://source.puri.sm/Librem5/uboot-imx/blob/busfreq/board/purism/librem5_devkit/lpddr4_timing_b0.c#L1365 Does 100 MHz and 25 MHz not work on B0 ? I added the ddrc_and noc opp as well as the 166MHz opp https://source.puri.sm/angus.ainslie/linux-next/blob/busfreq/arch/arm64/boot/dts/freescale/imx8mq.dtsi#L214 I also added the interconnects ( do we need them on imx8mq ? ) https://source.puri.sm/angus.ainslie/linux-next/blob/busfreq/arch/arm64/boot/dts/freescale/imx8mq.dtsi#L990 I had to add a hack as the PM QoS was limiting the bus speed to 399MHz , if you have any ideas why that would be appreciated. https://source.puri.sm/angus.ainslie/linux-next/blob/busfreq/drivers/devfreq/devfreq.c#L143 The driver is probing [ 12.136537] bus: 'platform': driver_probe_device: matched device 3d400000.dram-controller with driver imx-ddrc-devfrq [ 12.147259] bus: 'platform': really_probe: probing driver imx-ddrc-devfreq with device 3d400000.dram-controller [ 12.157382] imx-ddrc-devfreq 3d400000.dram-controller: no pinctrl handle [ 12.164197] arm_smcc rate 0 800000000 [ 12.167880] arm_smcc rate 1 166750000 [ 12.171778] of: _opp_add_static_v2: turbo:0 rate:25000000 uv:0 uvmin:0 uvmax:0 latency:0 [ 12.179994] of: _opp_add_static_v2: turbo:0 rate:100000000 uv:0 uvmin:0 uvmax:0 latency:0 [ 12.188311] of: _opp_add_static_v2: turbo:0 rate:166750000 uv:0 uvmin:0 uvmax:0 latency:0 [ 12.196606] of: _opp_add_static_v2: turbo:0 rate:800000000 uv:0 uvmin:0 uvmax:0 latency:0 [ 12.204930] imx-ddrc-devfreq 3d400000.dram-controller: events from pmu imx8_ddr0 [ 12.212403] Added freq 0 25000000 [ 12.215742] Added freq 1 100000000 [ 12.219177] Added freq 2 166750000 [ 12.222648] Added freq 3 800000000 [ 12.226105] device: 'devfreq0': device_add [ 12.230287] PM: Adding info for No Bus:devfreq0 [ 12.234864] driver: 'imx-ddrc-devfreq': driver_bound: bound to device '3d400000.dram-controller' [ 12.243699] bus: 'platform': really_probe: bound device 3d400000.dram-controller to driver imx-ddrc-devfreq Add seems to run correctly until it tries to adjust the clock to 166MHz [ 19.555482] ddrc checking rate 800000000 166750000 [ 19.555489] ddrc checking rate 166750000 166750000 [ 19.560442] bus: 'usb-serial': really_probe: bound device ttyUSB0 to driver option1 [ 19.568751] imx-ddrc-devfreq 3d400000.dram-controller: ddrc about to change freq 800000000 to 166750000 And the board hangs there. Any ideas on how to get past this ? Thanks Angus > martin > > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On 10.10.2019 17:43, Angus Ainslie wrote: >>>>> This adds a platform driver for the i.MX8MM SoC. >>>>> >>>>> Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> >>>>> Signed-off-by: Alexandre Bailon <abailon@baylibre.com> >>>>> --- >>>>> drivers/interconnect/imx/Kconfig | 4 + >>>>> drivers/interconnect/imx/Makefile | 1 + >>>>> drivers/interconnect/imx/imx8mm.c | 114 >>>>> ++++++++++++++++++++++ >>>>> include/dt-bindings/interconnect/imx8mm.h | 49 ++++++++++ >>>>> 4 files changed, 168 insertions(+) >>>>> create mode 100644 drivers/interconnect/imx/imx8mm.c >>>>> create mode 100644 include/dt-bindings/interconnect/imx8mm.h >>>> >>>> Do you plan to add such a driver for imx8mq too? >>> >>> Yes! The topology is different (serving different IP blocks) but no >>> functional code changes are required between 8mm 8mn 8mq. >> >> Thanks for the update, that's good to hear. I'll get back to you when I >> come around to test this and wish you good progress until then :) >> > I've taken up this work while Martin is on leave. > > I've integrated your u-boot and ATF on our board and I have a couple of > questions. Our board is running imx8mq B0 (Rev 2.0) silicon. > > It looks like this line limits the training frequencies to 800 MHz and > 166 MHz Yes! This is due to a hardware errata which was solved in B1: DRAM pll can't be disabled. This means that instead of 25/100/800 freqs are 166/800, and this requires code changes. > Does 100 MHz and 25 MHz not work on B0 ? No, lower rates require dram clk from a composite slice (dram_alt_root) > I added the ddrc_and noc opp as well as the 166MHz opp > > I also added the interconnects ( do we need them on imx8mq ? ) The interconnect stuff is not required to switch dram frequency, it's for device to make minimum bandwidth requests. It an additional feature on top. As a hack I configured FEC to do so but a saner example would be to request bandwidth based on display resolution and color depth. > I had to add a hack as the PM QoS was limiting the bus speed to 399MHz , > if you have any ideas why that would be appreciated. You probably need to set ethernet down (which is awkward) or better just drop the interconnect properties and test using the devfreq userspace governor. > The driver is probing > > [ 12.136537] bus: 'platform': driver_probe_device: matched device > 3d400000.dram-controller with driver imx-ddrc-devfrq > [ 12.147259] bus: 'platform': really_probe: probing driver > imx-ddrc-devfreq with device 3d400000.dram-controller > [ 12.157382] imx-ddrc-devfreq 3d400000.dram-controller: no pinctrl > handle > [ 12.164197] arm_smcc rate 0 800000000 > [ 12.167880] arm_smcc rate 1 166750000 > [ 12.171778] of: _opp_add_static_v2: turbo:0 rate:25000000 uv:0 > uvmin:0 uvmax:0 latency:0 > [ 12.179994] of: _opp_add_static_v2: turbo:0 rate:100000000 uv:0 > uvmin:0 uvmax:0 latency:0 > [ 12.188311] of: _opp_add_static_v2: turbo:0 rate:166750000 uv:0 > uvmin:0 uvmax:0 latency:0 > [ 12.196606] of: _opp_add_static_v2: turbo:0 rate:800000000 uv:0 > uvmin:0 uvmax:0 latency:0 > [ 12.204930] imx-ddrc-devfreq 3d400000.dram-controller: events from > pmu imx8_ddr0 > [ 12.212403] Added freq 0 25000000 > [ 12.215742] Added freq 1 100000000 > [ 12.219177] Added freq 2 166750000 > [ 12.222648] Added freq 3 800000000 > [ 12.226105] device: 'devfreq0': device_add > [ 12.230287] PM: Adding info for No Bus:devfreq0 > [ 12.234864] driver: 'imx-ddrc-devfreq': driver_bound: bound to device > '3d400000.dram-controller' > [ 12.243699] bus: 'platform': really_probe: bound device > 3d400000.dram-controller to driver imx-ddrc-devfreq > > Add seems to run correctly until it tries to adjust the clock to 166MHz > > [ 19.555482] ddrc checking rate 800000000 166750000 > [ 19.555489] ddrc checking rate 166750000 166750000 > [ 19.560442] bus: 'usb-serial': really_probe: bound device ttyUSB0 to > driver option1 > [ 19.568751] imx-ddrc-devfreq 3d400000.dram-controller: ddrc about to > change freq 800000000 to 166750000 > > And the board hangs there. Any ideas on how to get past this ? Please try this ATF patch: https://github.com/cdleonard/arm-trusted-firmware/commit/783fc2b2c4266bfdb5218e4d9b6b2bc90849e0e9 I tested switching on imx8mq-evk with B0 SoC but a few additional changes are required in kernel to support switching between rates which are both backed by PLL: * Mark the PLL CLK_GET_RATE_NOCACHE * Set the rate to 166935483 exactly (to match clk_get_rate) * Make the rounding in imx-ddrc more generous. I will integrate these changes into the next version. -- Regards, Leonard
On 2019-10-15 07:05, Leonard Crestez wrote: > On 10.10.2019 17:43, Angus Ainslie wrote: >> >> I've integrated your u-boot and ATF on our board and I have a couple >> of >> questions. Our board is running imx8mq B0 (Rev 2.0) silicon. >> >> It looks like this line limits the training frequencies to 800 MHz and >> 166 MHz > > Yes! This is due to a hardware errata which was solved in B1: DRAM pll > can't be disabled. This means that instead of 25/100/800 freqs are > 166/800, and this requires code changes. > >> Does 100 MHz and 25 MHz not work on B0 ? > > No, lower rates require dram clk from a composite slice (dram_alt_root) > >> I added the ddrc_and noc opp as well as the 166MHz opp >> >> I also added the interconnects ( do we need them on imx8mq ? ) > > The interconnect stuff is not required to switch dram frequency, it's > for device to make minimum bandwidth requests. It an additional feature > on top. > > As a hack I configured FEC to do so but a saner example would be to > request bandwidth based on display resolution and color depth. > >> I had to add a hack as the PM QoS was limiting the bus speed to 399MHz >> , >> if you have any ideas why that would be appreciated. > > You probably need to set ethernet down (which is awkward) or better > just > drop the interconnect properties and test using the devfreq userspace > governor. > >> The driver is probing >> >> [ 12.136537] bus: 'platform': driver_probe_device: matched device >> 3d400000.dram-controller with driver imx-ddrc-devfrq >> [ 12.147259] bus: 'platform': really_probe: probing driver >> imx-ddrc-devfreq with device 3d400000.dram-controller >> [ 12.157382] imx-ddrc-devfreq 3d400000.dram-controller: no pinctrl >> handle >> [ 12.164197] arm_smcc rate 0 800000000 >> [ 12.167880] arm_smcc rate 1 166750000 >> [ 12.171778] of: _opp_add_static_v2: turbo:0 rate:25000000 uv:0 >> uvmin:0 uvmax:0 latency:0 >> [ 12.179994] of: _opp_add_static_v2: turbo:0 rate:100000000 uv:0 >> uvmin:0 uvmax:0 latency:0 >> [ 12.188311] of: _opp_add_static_v2: turbo:0 rate:166750000 uv:0 >> uvmin:0 uvmax:0 latency:0 >> [ 12.196606] of: _opp_add_static_v2: turbo:0 rate:800000000 uv:0 >> uvmin:0 uvmax:0 latency:0 >> [ 12.204930] imx-ddrc-devfreq 3d400000.dram-controller: events from >> pmu imx8_ddr0 >> [ 12.212403] Added freq 0 25000000 >> [ 12.215742] Added freq 1 100000000 >> [ 12.219177] Added freq 2 166750000 >> [ 12.222648] Added freq 3 800000000 >> [ 12.226105] device: 'devfreq0': device_add >> [ 12.230287] PM: Adding info for No Bus:devfreq0 >> [ 12.234864] driver: 'imx-ddrc-devfreq': driver_bound: bound to >> device >> '3d400000.dram-controller' >> [ 12.243699] bus: 'platform': really_probe: bound device >> 3d400000.dram-controller to driver imx-ddrc-devfreq >> >> Add seems to run correctly until it tries to adjust the clock to >> 166MHz >> >> [ 19.555482] ddrc checking rate 800000000 166750000 >> [ 19.555489] ddrc checking rate 166750000 166750000 >> [ 19.560442] bus: 'usb-serial': really_probe: bound device ttyUSB0 >> to >> driver option1 >> [ 19.568751] imx-ddrc-devfreq 3d400000.dram-controller: ddrc about >> to >> change freq 800000000 to 166750000 >> >> And the board hangs there. Any ideas on how to get past this ? > > Please try this ATF patch: > > https://github.com/cdleonard/arm-trusted-firmware/commit/783fc2b2c4266bfdb5218e4d9b6b2bc90849e0e9 > Ok applied this to the tree we're using https://source.puri.sm/Librem5/arm-trusted-firmware/commit/783fc2b2c4266bfdb5218e4d9b6b2bc90849e0e9 > I tested switching on imx8mq-evk with B0 SoC but a few additional > changes are required in kernel to support switching between rates which > are both backed by PLL: > > * Mark the PLL CLK_GET_RATE_NOCACHE Is this what you meant ? diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c index 2813884f69c1..e5f50cf8a264 100644 --- a/drivers/clk/imx/clk-imx8mq.c +++ b/drivers/clk/imx/clk-imx8mq.c @@ -345,7 +345,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) clks[IMX8MQ_SYS1_PLL_OUT] = imx_clk_sccg_pll("sys1_pll_out", sys1_pll_out_sels, ARRAY_SIZE(sys1_pll_out_sels), 0, 0, 0, base + 0x30, CLK_IS_CRITICAL); clks[IMX8MQ_SYS2_PLL_OUT] = imx_clk_sccg_pll("sys2_pll_out", sys2_pll_out_sels, ARRAY_SIZE(sys2_pll_out_sels), 0, 0, 1, base + 0x3c, CLK_IS_CRITICAL); clks[IMX8MQ_SYS3_PLL_OUT] = imx_clk_sccg_pll("sys3_pll_out", sys3_pll_out_sels, ARRAY_SIZE(sys3_pll_out_sels), 0, 0, 1, base + 0x48, CLK_IS_CRITICAL); - clks[IMX8MQ_DRAM_PLL_OUT] = imx_clk_sccg_pll("dram_pll_out", dram_pll_out_sels, ARRAY_SIZE(dram_pll_out_sels), 0, 0, 0, base + 0x60, CLK_IS_CRITICAL); + clks[IMX8MQ_DRAM_PLL_OUT] = imx_clk_sccg_pll("dram_pll_out", dram_pll_out_sels, ARRAY_SIZE(dram_pll_out_sels), 0, 0, 0, base + 0x60, CLK_IS_CRITICAL|CLK_GET_RATE_NOCACHE); /* SYS PLL1 fixed output */ clks[IMX8MQ_SYS1_PLL_40M_CG] = imx_clk_gate("sys1_pll_40m_cg", "sys1_pll_out", base + 0x30, 9); > * Set the rate to 166935483 exactly (to match clk_get_rate) Okay I hacked that in diff --git a/drivers/devfreq/imx-ddrc.c b/drivers/devfreq/imx-ddrc.c index 4eed6f50bb8d..a832768a865f 100644 --- a/drivers/devfreq/imx-ddrc.c +++ b/drivers/devfreq/imx-ddrc.c @@ -436,6 +436,10 @@ static int imx_ddrc_init_freq_info(struct device *dev) return -ENODEV; } + /* B0 hack */ + if ( freq->rate == 166750000 ) + freq->rate = 166935483; + pr_err( "arm_smcc rate %d %lu\n", index, freq->rate ); } --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -211,7 +211,7 @@ opp-hz = /bits/ 64 <100000000>; }; opp-166M { - opp-hz = /bits/ 64 <166750000>; + opp-hz = /bits/ 64 <166935483>; }; opp-800M { opp-hz = /bits/ 64 <800000000>; > * Make the rounding in imx-ddrc more generous. Sorry I don't understand what you mean by this. Adding the other changes the board no longer hangs when trying to change frequencies but it also doesn't seem to actually change the frequency. [ 3.076426] ddrc checking rate 800000000 166935483 [ 3.081290] ddrc checking rate 166935483 166935483 [ 3.086225] imx-ddrc-devfreq 3d400000.dram-controller: ddrc about to change freq 800000000 to 166935483 [ 3.086891] imx-ddrc-devfreq 3d400000.dram-controller: ddrc changed freq 800000000 to 166935483 root@pureos:~# cat /sys/class/devfreq/devfreq0/cur_freq 800000000 root@pureos:~# cat /sys/class/devfreq/devfreq0/target_freq 166935483 Is this the missing rounding or is there something else missing ? Thanks Angus > > I will integrate these changes into the next version. > > -- > Regards, > Leonard
On 16.10.2019 17:09, Angus Ainslie wrote: > On 2019-10-15 07:05, Leonard Crestez wrote: >> On 10.10.2019 17:43, Angus Ainslie wrote: >>> >>> I've integrated your u-boot and ATF on our board and I have a couple >>> of questions. Our board is running imx8mq B0 (Rev 2.0) silicon. >>> >>> It looks like this line limits the training frequencies to 800 MHz and >>> 166 MHz >> >> Yes! This is due to a hardware errata which was solved in B1: DRAM pll >> can't be disabled. This means that instead of 25/100/800 freqs are >> 166/800, and this requires code changes. >> >>> Does 100 MHz and 25 MHz not work on B0 ? >> >> No, lower rates require dram clk from a composite slice (dram_alt_root) >> >>> I added the ddrc_and noc opp as well as the 166MHz opp >>> >>> I also added the interconnects ( do we need them on imx8mq ? ) >> >> The interconnect stuff is not required to switch dram frequency, it's >> for device to make minimum bandwidth requests. It an additional feature >> on top. >> >> As a hack I configured FEC to do so but a saner example would be to >> request bandwidth based on display resolution and color depth. >> >>> I had to add a hack as the PM QoS was limiting the bus speed to 399MHz, >>> if you have any ideas why that would be appreciated. >> >> You probably need to set ethernet down (which is awkward) or better >> just drop the interconnect properties and test using the devfreq userspace >> governor. >> >>> The driver is probing >>> >>> [ 12.136537] bus: 'platform': driver_probe_device: matched device >>> 3d400000.dram-controller with driver imx-ddrc-devfrq >>> [ 12.147259] bus: 'platform': really_probe: probing driver >>> imx-ddrc-devfreq with device 3d400000.dram-controller >>> [ 12.157382] imx-ddrc-devfreq 3d400000.dram-controller: no pinctrl >>> handle >>> [ 12.164197] arm_smcc rate 0 800000000 >>> [ 12.167880] arm_smcc rate 1 166750000 >>> [ 12.171778] of: _opp_add_static_v2: turbo:0 rate:25000000 uv:0 >>> uvmin:0 uvmax:0 latency:0 >>> [ 12.179994] of: _opp_add_static_v2: turbo:0 rate:100000000 uv:0 >>> uvmin:0 uvmax:0 latency:0 >>> [ 12.188311] of: _opp_add_static_v2: turbo:0 rate:166750000 uv:0 >>> uvmin:0 uvmax:0 latency:0 >>> [ 12.196606] of: _opp_add_static_v2: turbo:0 rate:800000000 uv:0 >>> uvmin:0 uvmax:0 latency:0 >>> [ 12.204930] imx-ddrc-devfreq 3d400000.dram-controller: events from >>> pmu imx8_ddr0 >>> [ 12.212403] Added freq 0 25000000 >>> [ 12.215742] Added freq 1 100000000 >>> [ 12.219177] Added freq 2 166750000 >>> [ 12.222648] Added freq 3 800000000 >>> [ 12.226105] device: 'devfreq0': device_add >>> [ 12.230287] PM: Adding info for No Bus:devfreq0 >>> [ 12.234864] driver: 'imx-ddrc-devfreq': driver_bound: bound to >>> device >>> '3d400000.dram-controller' >>> [ 12.243699] bus: 'platform': really_probe: bound device >>> 3d400000.dram-controller to driver imx-ddrc-devfreq >>> >>> Add seems to run correctly until it tries to adjust the clock to >>> 166MHz >>> >>> [ 19.555482] ddrc checking rate 800000000 166750000 >>> [ 19.555489] ddrc checking rate 166750000 166750000 >>> [ 19.560442] bus: 'usb-serial': really_probe: bound device ttyUSB0 >>> to >>> driver option1 >>> [ 19.568751] imx-ddrc-devfreq 3d400000.dram-controller: ddrc about >>> to >>> change freq 800000000 to 166750000 >>> >>> And the board hangs there. Any ideas on how to get past this ? >> >> Please try this ATF patch: > > Ok applied this to the tree we're using > >> I tested switching on imx8mq-evk with B0 SoC but a few additional >> changes are required in kernel to support switching between rates which >> are both backed by PLL: >> >> * Mark the PLL CLK_GET_RATE_NOCACHE > > Is this what you meant ? > > diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c > index 2813884f69c1..e5f50cf8a264 100644 > --- a/drivers/clk/imx/clk-imx8mq.c > +++ b/drivers/clk/imx/clk-imx8mq.c > @@ -345,7 +345,7 @@ static int imx8mq_clocks_probe(struct > platform_device *pdev) > clks[IMX8MQ_SYS1_PLL_OUT] = imx_clk_sccg_pll("sys1_pll_out", > sys1_pll_out_sels, ARRAY_SIZE(sys1_pll_out_sels), 0, 0, 0, base + 0x30, > CLK_IS_CRITICAL); > clks[IMX8MQ_SYS2_PLL_OUT] = imx_clk_sccg_pll("sys2_pll_out", > sys2_pll_out_sels, ARRAY_SIZE(sys2_pll_out_sels), 0, 0, 1, base + 0x3c, > CLK_IS_CRITICAL); > clks[IMX8MQ_SYS3_PLL_OUT] = imx_clk_sccg_pll("sys3_pll_out", > sys3_pll_out_sels, ARRAY_SIZE(sys3_pll_out_sels), 0, 0, 1, base + 0x48, > CLK_IS_CRITICAL); > - clks[IMX8MQ_DRAM_PLL_OUT] = imx_clk_sccg_pll("dram_pll_out", > dram_pll_out_sels, ARRAY_SIZE(dram_pll_out_sels), 0, 0, 0, base + 0x60, > CLK_IS_CRITICAL); > + clks[IMX8MQ_DRAM_PLL_OUT] = imx_clk_sccg_pll("dram_pll_out", > dram_pll_out_sels, ARRAY_SIZE(dram_pll_out_sels), 0, 0, 0, base + 0x60, > CLK_IS_CRITICAL|CLK_GET_RATE_NOCACHE); Yes. >> * Set the rate to 166935483 exactly (to match clk_get_rate) > > Okay I hacked that in > > diff --git a/drivers/devfreq/imx-ddrc.c b/drivers/devfreq/imx-ddrc.c > index 4eed6f50bb8d..a832768a865f 100644 > --- a/drivers/devfreq/imx-ddrc.c > +++ b/drivers/devfreq/imx-ddrc.c > @@ -436,6 +436,10 @@ static int imx_ddrc_init_freq_info(struct device > *dev) > return -ENODEV; > } > > + /* B0 hack */ > + if ( freq->rate == 166750000 ) > + freq->rate = 166935483; > +inserting > pr_err( "arm_smcc rate %d %lu\n", index, freq->rate ); > } A nicer solution would be to keep imx_ddrc_freq.rate in MT/s as reported by firmware and divide by 25000 in imx_ddrc_find_freq instead. > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > @@ -211,7 +211,7 @@ > opp-hz = /bits/ 64 <100000000>; > }; > opp-166M { > - opp-hz = /bits/ 64 <166750000>; > + opp-hz = /bits/ 64 <166935483>; > }; > opp-800M { > opp-hz = /bits/ 64 <800000000>; Yes, this is the precise clock rate in Hz. >> * Make the rounding in imx-ddrc more generous. > > Sorry I don't understand what you mean by this I meant to make imx_ddrc_find_freq find 667 MT/s for an OPP of 166935483: /* * Firmware reports values in MT/s, so we round-down from Hz * Rounding is extra generous to ensure a match. */ rate = DIV_ROUND_CLOSEST(rate, 250000); for (i = 0; i < priv->freq_count; ++i) { struct imx_ddrc_freq *freq = &priv->freq_table[i]; if (freq->rate == rate || freq->rate + 1 == rate || freq->rate - 1 == rate) return freq; } But your B0 hack above should also work. > Adding the other changes the board no longer hangs when trying to change > frequencies but it also doesn't seem to actually change the frequency. > > [ 3.076426] ddrc checking rate 800000000 166935483 > [ 3.081290] ddrc checking rate 166935483 166935483 > [ 3.086225] imx-ddrc-devfreq 3d400000.dram-controller: ddrc about to > change freq 800000000 to 166935483 > [ 3.086891] imx-ddrc-devfreq 3d400000.dram-controller: ddrc changed > freq 800000000 to 166935483 > > root@pureos:~# cat /sys/class/devfreq/devfreq0/cur_freq > 800000000 > root@pureos:~# cat /sys/class/devfreq/devfreq0/target_freq > 166935483 The target_freq value is from clk_get_rate(dram_core) but it is dram_core's parent which gets updated. It seems that a clk mux ignores CLK_GET_RATE_NOCACHE on the parent. An update can be forced by adding `clk_get_rate(new_dram_core_parent);` at the end of imx_ddrc_set_freq. You should also be able to check by looking at clk_summary or /sys/kernel/debug/clk/dram_core_clk/clk_rate /sys/kernel/debug/clk/dram_pll_out/clk_rate -- Regards, Leonard
On 2019-10-16 07:54, Leonard Crestez wrote: > On 16.10.2019 17:09, Angus Ainslie wrote: >> On 2019-10-15 07:05, Leonard Crestez wrote: >>> On 10.10.2019 17:43, Angus Ainslie wrote: >>>> >>>> I've integrated your u-boot and ATF on our board and I have a couple >>>> of questions. Our board is running imx8mq B0 (Rev 2.0) silicon. >>>> >>>> It looks like this line limits the training frequencies to 800 MHz >>>> and >>>> 166 MHz >>> >>> Yes! This is due to a hardware errata which was solved in B1: DRAM >>> pll >>> can't be disabled. This means that instead of 25/100/800 freqs are >>> 166/800, and this requires code changes. >>> >>>> Does 100 MHz and 25 MHz not work on B0 ? >>> >>> No, lower rates require dram clk from a composite slice >>> (dram_alt_root) >>> >>>> I added the ddrc_and noc opp as well as the 166MHz opp >>>> >>>> I also added the interconnects ( do we need them on imx8mq ? ) >>> >>> The interconnect stuff is not required to switch dram frequency, it's >>> for device to make minimum bandwidth requests. It an additional >>> feature >>> on top. >>> >>> As a hack I configured FEC to do so but a saner example would be to >>> request bandwidth based on display resolution and color depth. >>> >>>> I had to add a hack as the PM QoS was limiting the bus speed to >>>> 399MHz, >>>> if you have any ideas why that would be appreciated. >>> >>> You probably need to set ethernet down (which is awkward) or better >>> just drop the interconnect properties and test using the devfreq >>> userspace >>> governor. >>> >>>> The driver is probing >>>> >>>> [ 12.136537] bus: 'platform': driver_probe_device: matched device >>>> 3d400000.dram-controller with driver imx-ddrc-devfrq >>>> [ 12.147259] bus: 'platform': really_probe: probing driver >>>> imx-ddrc-devfreq with device 3d400000.dram-controller >>>> [ 12.157382] imx-ddrc-devfreq 3d400000.dram-controller: no pinctrl >>>> handle >>>> [ 12.164197] arm_smcc rate 0 800000000 >>>> [ 12.167880] arm_smcc rate 1 166750000 >>>> [ 12.171778] of: _opp_add_static_v2: turbo:0 rate:25000000 uv:0 >>>> uvmin:0 uvmax:0 latency:0 >>>> [ 12.179994] of: _opp_add_static_v2: turbo:0 rate:100000000 uv:0 >>>> uvmin:0 uvmax:0 latency:0 >>>> [ 12.188311] of: _opp_add_static_v2: turbo:0 rate:166750000 uv:0 >>>> uvmin:0 uvmax:0 latency:0 >>>> [ 12.196606] of: _opp_add_static_v2: turbo:0 rate:800000000 uv:0 >>>> uvmin:0 uvmax:0 latency:0 >>>> [ 12.204930] imx-ddrc-devfreq 3d400000.dram-controller: events >>>> from >>>> pmu imx8_ddr0 >>>> [ 12.212403] Added freq 0 25000000 >>>> [ 12.215742] Added freq 1 100000000 >>>> [ 12.219177] Added freq 2 166750000 >>>> [ 12.222648] Added freq 3 800000000 >>>> [ 12.226105] device: 'devfreq0': device_add >>>> [ 12.230287] PM: Adding info for No Bus:devfreq0 >>>> [ 12.234864] driver: 'imx-ddrc-devfreq': driver_bound: bound to >>>> device >>>> '3d400000.dram-controller' >>>> [ 12.243699] bus: 'platform': really_probe: bound device >>>> 3d400000.dram-controller to driver imx-ddrc-devfreq >>>> >>>> Add seems to run correctly until it tries to adjust the clock to >>>> 166MHz >>>> >>>> [ 19.555482] ddrc checking rate 800000000 166750000 >>>> [ 19.555489] ddrc checking rate 166750000 166750000 >>>> [ 19.560442] bus: 'usb-serial': really_probe: bound device ttyUSB0 >>>> to >>>> driver option1 >>>> [ 19.568751] imx-ddrc-devfreq 3d400000.dram-controller: ddrc about >>>> to >>>> change freq 800000000 to 166750000 >>>> >>>> And the board hangs there. Any ideas on how to get past this ? >>> >>> Please try this ATF patch: >> >> Ok applied this to the tree we're using >> >>> I tested switching on imx8mq-evk with B0 SoC but a few additional >>> changes are required in kernel to support switching between rates >>> which >>> are both backed by PLL: >>> >>> * Mark the PLL CLK_GET_RATE_NOCACHE >> >> Is this what you meant ? >> >> diff --git a/drivers/clk/imx/clk-imx8mq.c >> b/drivers/clk/imx/clk-imx8mq.c >> index 2813884f69c1..e5f50cf8a264 100644 >> --- a/drivers/clk/imx/clk-imx8mq.c >> +++ b/drivers/clk/imx/clk-imx8mq.c >> @@ -345,7 +345,7 @@ static int imx8mq_clocks_probe(struct >> platform_device *pdev) >> clks[IMX8MQ_SYS1_PLL_OUT] = imx_clk_sccg_pll("sys1_pll_out", >> sys1_pll_out_sels, ARRAY_SIZE(sys1_pll_out_sels), 0, 0, 0, base + >> 0x30, >> CLK_IS_CRITICAL); >> clks[IMX8MQ_SYS2_PLL_OUT] = imx_clk_sccg_pll("sys2_pll_out", >> sys2_pll_out_sels, ARRAY_SIZE(sys2_pll_out_sels), 0, 0, 1, base + >> 0x3c, >> CLK_IS_CRITICAL); >> clks[IMX8MQ_SYS3_PLL_OUT] = imx_clk_sccg_pll("sys3_pll_out", >> sys3_pll_out_sels, ARRAY_SIZE(sys3_pll_out_sels), 0, 0, 1, base + >> 0x48, >> CLK_IS_CRITICAL); >> - clks[IMX8MQ_DRAM_PLL_OUT] = imx_clk_sccg_pll("dram_pll_out", >> dram_pll_out_sels, ARRAY_SIZE(dram_pll_out_sels), 0, 0, 0, base + >> 0x60, >> CLK_IS_CRITICAL); >> + clks[IMX8MQ_DRAM_PLL_OUT] = imx_clk_sccg_pll("dram_pll_out", >> dram_pll_out_sels, ARRAY_SIZE(dram_pll_out_sels), 0, 0, 0, base + >> 0x60, >> CLK_IS_CRITICAL|CLK_GET_RATE_NOCACHE); > > Yes. > >>> * Set the rate to 166935483 exactly (to match clk_get_rate) >> >> Okay I hacked that in >> >> diff --git a/drivers/devfreq/imx-ddrc.c b/drivers/devfreq/imx-ddrc.c >> index 4eed6f50bb8d..a832768a865f 100644 >> --- a/drivers/devfreq/imx-ddrc.c >> +++ b/drivers/devfreq/imx-ddrc.c >> @@ -436,6 +436,10 @@ static int imx_ddrc_init_freq_info(struct device >> *dev) >> return -ENODEV; >> } >> >> + /* B0 hack */ >> + if ( freq->rate == 166750000 ) >> + freq->rate = 166935483; >> +inserting >> pr_err( "arm_smcc rate %d %lu\n", index, freq->rate >> ); >> } > > A nicer solution would be to keep imx_ddrc_freq.rate in MT/s as > reported > by firmware and divide by 25000 in imx_ddrc_find_freq instead. > >> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi >> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi >> @@ -211,7 +211,7 @@ >> opp-hz = /bits/ 64 <100000000>; >> }; >> opp-166M { >> - opp-hz = /bits/ 64 <166750000>; >> + opp-hz = /bits/ 64 <166935483>; >> }; >> opp-800M { >> opp-hz = /bits/ 64 <800000000>; > > Yes, this is the precise clock rate in Hz. > >>> * Make the rounding in imx-ddrc more generous. >> >> Sorry I don't understand what you mean by this > > I meant to make imx_ddrc_find_freq find 667 MT/s for an OPP of > 166935483: > > /* > * Firmware reports values in MT/s, so we round-down from Hz > * Rounding is extra generous to ensure a match. > */ > rate = DIV_ROUND_CLOSEST(rate, 250000); > for (i = 0; i < priv->freq_count; ++i) { > struct imx_ddrc_freq *freq = &priv->freq_table[i]; > if (freq->rate == rate || > freq->rate + 1 == rate || > freq->rate - 1 == rate) > return freq; > } > > But your B0 hack above should also work. > Thanks with those additions the driver is working on imx8mq B0. There is a small adjustment to the code above because you're scaling the rate you also need to scale the matching rate. --- a/drivers/devfreq/imx-ddrc.c +++ b/drivers/devfreq/imx-ddrc.c @@ -106,9 +106,17 @@ static struct imx_ddrc_freq *imx_ddrc_find_freq(struct imx_ddrc *priv, { int i; + /* + * Firmware reports values in MT/s, so we round-down from Hz + * Rounding is extra generous to ensure a match. + */ + rate = DIV_ROUND_CLOSEST(rate, 250000); for (i = 0; i < priv->freq_count; ++i) { - if (priv->freq_table[i].rate == rate) + struct imx_ddrc_freq *freq = &priv->freq_table[i]; + unsigned long match_rate = DIV_ROUND_CLOSEST(freq->rate,250000); + if (match_rate + 1 >= rate && + match_rate - 1 <= rate) return &priv->freq_table[i]; } Cheers Angus >> Adding the other changes the board no longer hangs when trying to >> change >> frequencies but it also doesn't seem to actually change the frequency. >> >> [ 3.076426] ddrc checking rate 800000000 166935483 >> [ 3.081290] ddrc checking rate 166935483 166935483 >> [ 3.086225] imx-ddrc-devfreq 3d400000.dram-controller: ddrc about >> to >> change freq 800000000 to 166935483 >> [ 3.086891] imx-ddrc-devfreq 3d400000.dram-controller: ddrc changed >> freq 800000000 to 166935483 >> >> root@pureos:~# cat /sys/class/devfreq/devfreq0/cur_freq >> 800000000 >> root@pureos:~# cat /sys/class/devfreq/devfreq0/target_freq >> 166935483 > > The target_freq value is from clk_get_rate(dram_core) but it is > dram_core's parent which gets updated. It seems that a clk mux ignores > CLK_GET_RATE_NOCACHE on the parent. > > An update can be forced by adding `clk_get_rate(new_dram_core_parent);` > at the end of imx_ddrc_set_freq. > > You should also be able to check by looking at clk_summary or > /sys/kernel/debug/clk/dram_core_clk/clk_rate > /sys/kernel/debug/clk/dram_pll_out/clk_rate > > -- > Regards, > Leonard
diff --git a/drivers/interconnect/imx/Kconfig b/drivers/interconnect/imx/Kconfig index 45fbae7007af..2f06cb1f81c3 100644 --- a/drivers/interconnect/imx/Kconfig +++ b/drivers/interconnect/imx/Kconfig @@ -1,5 +1,9 @@ config INTERCONNECT_IMX bool "i.MX interconnect drivers" depends on ARCH_MXC || ARCH_MXC_ARM64 || COMPILE_TEST help Generic interconnect driver for i.MX SOCs + +config INTERCONNECT_IMX8MM + def_bool y + depends on INTERCONNECT_IMX diff --git a/drivers/interconnect/imx/Makefile b/drivers/interconnect/imx/Makefile index bb92fd9fe4a5..5f658c1608a6 100644 --- a/drivers/interconnect/imx/Makefile +++ b/drivers/interconnect/imx/Makefile @@ -1 +1,2 @@ obj-$(CONFIG_INTERCONNECT_IMX) += imx.o +obj-$(CONFIG_INTERCONNECT_IMX8MM) += imx8mm.o diff --git a/drivers/interconnect/imx/imx8mm.c b/drivers/interconnect/imx/imx8mm.c new file mode 100644 index 000000000000..5bed7babff96 --- /dev/null +++ b/drivers/interconnect/imx/imx8mm.c @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Interconnect framework driver for i.MX SoC + * + * Copyright (c) 2019, BayLibre + * Copyright (c) 2019, NXP + * Author: Alexandre Bailon <abailon@baylibre.com> + * Author: Leonard Crestez <leonard.crestez@nxp.com> + */ + +#include <linux/device.h> +#include <linux/module.h> +#include <linux/of_platform.h> +#include <linux/platform_device.h> + +#include <dt-bindings/interconnect/imx8mm.h> + +#include "imx.h" + +static const struct imx_icc_node_adj_desc imx8mm_dram_adj = { + .devfreq_name = "dram", + .bw_mul = 1, + .bw_div = 16, +}; + +static const struct imx_icc_node_adj_desc imx8mm_noc_adj = { + .devfreq_name = "noc", + .bw_mul = 1, + .bw_div = 16, +}; + +/* + * Describe bus masters, slaves and connections between them + * + * This is a simplified subset of the bus diagram, there are several other + * PL301 nics which are skipped/merged into PL301_MAIN + */ +static struct imx_icc_node_desc nodes[] = { + DEFINE_BUS_INTERCONNECT("NOC", IMX8MM_ICN_NOC, &imx8mm_noc_adj, + 2, IMX8MM_ICS_DRAM, IMX8MM_ICN_MAIN), + + DEFINE_BUS_SLAVE("DRAM", IMX8MM_ICS_DRAM, &imx8mm_dram_adj), + DEFINE_BUS_SLAVE("OCRAM", IMX8MM_ICS_OCRAM, NULL), + DEFINE_BUS_MASTER("A53", IMX8MM_ICM_A53, IMX8MM_ICN_NOC), + + /* VPUMIX */ + DEFINE_BUS_MASTER("VPU H1", IMX8MM_ICM_VPU_H1, IMX8MM_ICN_VIDEO), + DEFINE_BUS_MASTER("VPU G1", IMX8MM_ICM_VPU_G1, IMX8MM_ICN_VIDEO), + DEFINE_BUS_MASTER("VPU G2", IMX8MM_ICM_VPU_G2, IMX8MM_ICN_VIDEO), + DEFINE_BUS_INTERCONNECT("PL301_VIDEO", IMX8MM_ICN_VIDEO, NULL, 1, IMX8MM_ICN_NOC), + + /* GPUMIX */ + DEFINE_BUS_MASTER("GPU 2D", IMX8MM_ICM_GPU2D, IMX8MM_ICN_GPU), + DEFINE_BUS_MASTER("GPU 3D", IMX8MM_ICM_GPU3D, IMX8MM_ICN_GPU), + DEFINE_BUS_INTERCONNECT("PL301_GPU", IMX8MM_ICN_GPU, NULL, 1, IMX8MM_ICN_NOC), + + /* DISPLAYMIX */ + DEFINE_BUS_MASTER("CSI", IMX8MM_ICM_CSI, IMX8MM_ICN_MIPI), + DEFINE_BUS_MASTER("LCDIF", IMX8MM_ICM_LCDIF, IMX8MM_ICN_MIPI), + DEFINE_BUS_INTERCONNECT("PL301_MIPI", IMX8MM_ICN_MIPI, NULL, 1, IMX8MM_ICN_NOC), + + /* HSIO */ + DEFINE_BUS_MASTER("USB1", IMX8MM_ICM_USB1, IMX8MM_ICN_HSIO), + DEFINE_BUS_MASTER("USB2", IMX8MM_ICM_USB2, IMX8MM_ICN_HSIO), + DEFINE_BUS_MASTER("PCIE", IMX8MM_ICM_PCIE, IMX8MM_ICN_HSIO), + DEFINE_BUS_INTERCONNECT("PL301_HSIO", IMX8MM_ICN_HSIO, NULL, 1, IMX8MM_ICN_NOC), + + /* Audio */ + DEFINE_BUS_MASTER("SDMA2", IMX8MM_ICM_SDMA2, IMX8MM_ICN_AUDIO), + DEFINE_BUS_MASTER("SDMA3", IMX8MM_ICM_SDMA3, IMX8MM_ICN_AUDIO), + DEFINE_BUS_INTERCONNECT("PL301_AUDIO", IMX8MM_ICN_AUDIO, NULL, 1, IMX8MM_ICN_MAIN), + + /* Ethernet */ + DEFINE_BUS_MASTER("ENET", IMX8MM_ICM_ENET, IMX8MM_ICN_ENET), + DEFINE_BUS_INTERCONNECT("PL301_ENET", IMX8MM_ICN_ENET, NULL, 1, IMX8MM_ICN_MAIN), + + /* Other */ + DEFINE_BUS_MASTER("SDMA1", IMX8MM_ICM_SDMA1, IMX8MM_ICN_MAIN), + DEFINE_BUS_MASTER("NAND", IMX8MM_ICM_NAND, IMX8MM_ICN_MAIN), + DEFINE_BUS_MASTER("USDHC1", IMX8MM_ICM_USDHC1, IMX8MM_ICN_MAIN), + DEFINE_BUS_MASTER("USDHC2", IMX8MM_ICM_USDHC2, IMX8MM_ICN_MAIN), + DEFINE_BUS_MASTER("USDHC3", IMX8MM_ICM_USDHC3, IMX8MM_ICN_MAIN), + DEFINE_BUS_INTERCONNECT("PL301_MAIN", IMX8MM_ICN_MAIN, NULL, + 2, IMX8MM_ICN_NOC, IMX8MM_ICS_OCRAM), +}; + +static int imx8mm_icc_probe(struct platform_device *pdev) +{ + return imx_icc_register(pdev, nodes, ARRAY_SIZE(nodes)); +} + +static int imx8mm_icc_remove(struct platform_device *pdev) +{ + return imx_icc_unregister(pdev); +} + +static const struct of_device_id imx_icc_of_match[] = { + { .compatible = "fsl,imx8mm-interconnect" }, + { }, +}; +MODULE_DEVICE_TABLE(of, imx_icc_of_match); + +static struct platform_driver imx8mm_icc_driver = { + .probe = imx8mm_icc_probe, + .remove = imx8mm_icc_remove, + .driver = { + .name = "imx8mm-interconnect", + .of_match_table = imx_icc_of_match, + }, +}; + +builtin_platform_driver(imx8mm_icc_driver); +MODULE_AUTHOR("Alexandre Bailon <abailon@baylibre.com>"); +MODULE_LICENSE("GPL v2"); diff --git a/include/dt-bindings/interconnect/imx8mm.h b/include/dt-bindings/interconnect/imx8mm.h new file mode 100644 index 000000000000..5404f2af15c3 --- /dev/null +++ b/include/dt-bindings/interconnect/imx8mm.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Interconnect framework driver for i.MX SoC + * + * Copyright (c) 2019, BayLibre + * Author: Alexandre Bailon <abailon@baylibre.com> + */ + +#ifndef __IMX8MM_ICM_INTERCONNECT_IDS_H +#define __IMX8MM_ICM_INTERCONNECT_IDS_H + +#define IMX8MM_ICN_NOC 1 +#define IMX8MM_ICS_DRAM 2 +#define IMX8MM_ICS_OCRAM 3 +#define IMX8MM_ICM_A53 4 + +#define IMX8MM_ICM_VPU_H1 5 +#define IMX8MM_ICM_VPU_G1 6 +#define IMX8MM_ICM_VPU_G2 7 +#define IMX8MM_ICN_VIDEO 8 + +#define IMX8MM_ICM_GPU2D 9 +#define IMX8MM_ICM_GPU3D 10 +#define IMX8MM_ICN_GPU 11 + +#define IMX8MM_ICM_CSI 12 +#define IMX8MM_ICM_LCDIF 13 +#define IMX8MM_ICN_MIPI 14 + +#define IMX8MM_ICM_USB1 15 +#define IMX8MM_ICM_USB2 16 +#define IMX8MM_ICM_PCIE 17 +#define IMX8MM_ICN_HSIO 18 + +#define IMX8MM_ICM_SDMA2 19 +#define IMX8MM_ICM_SDMA3 20 +#define IMX8MM_ICN_AUDIO 21 + +#define IMX8MM_ICN_ENET 22 +#define IMX8MM_ICM_ENET 23 + +#define IMX8MM_ICN_MAIN 24 +#define IMX8MM_ICM_NAND 25 +#define IMX8MM_ICM_SDMA1 26 +#define IMX8MM_ICM_USDHC1 27 +#define IMX8MM_ICM_USDHC2 28 +#define IMX8MM_ICM_USDHC3 29 + +#endif /* __IMX8MM_ICM_INTERCONNECT_IDS_H */