From patchwork Mon Jan 26 07:56:11 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Baruch Siach X-Patchwork-Id: 5707081 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id B0666C058E for ; Mon, 26 Jan 2015 08:00:51 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id BB84C2012B for ; Mon, 26 Jan 2015 08:00:50 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C4C02200F0 for ; Mon, 26 Jan 2015 08:00:49 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YFeYy-00031u-SH; Mon, 26 Jan 2015 07:58:24 +0000 Received: from guitar.tcltek.co.il ([192.115.133.116] helo=mx.tkos.co.il) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YFeYU-0002UA-PL for linux-arm-kernel@lists.infradead.org; Mon, 26 Jan 2015 07:57:57 +0000 Received: from tarshish.tkos.co.il (unknown [10.0.8.6]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) by mx.tkos.co.il (Postfix) with ESMTPSA id 59207440A88; Mon, 26 Jan 2015 09:57:30 +0200 (IST) From: Baruch Siach To: Daniel Lezcano , Thomas Gleixner Subject: [PATCH v4 2/2] clocksource: driver for Conexant Digicolor SoC timer Date: Mon, 26 Jan 2015 09:56:11 +0200 Message-Id: X-Mailer: git-send-email 2.1.4 In-Reply-To: References: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150125_235755_367569_27C6779E X-CRM114-Status: GOOD ( 17.54 ) X-Spam-Score: 0.0 (/) Cc: Baruch Siach , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add clocksource driver to the Conexant CX92755 SoC, part of the Digicolor SoCs series. Hardware provides 8 timers, A to H. Timer A is dedicated to a future watchdog driver so we don't use it here. Use timer B for sched_clock, and timer C for clock_event. Signed-off-by: Baruch Siach --- drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-digicolor.c | 170 ++++++++++++++++++++++++++++++++++ 2 files changed, 171 insertions(+) create mode 100644 drivers/clocksource/timer-digicolor.c diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 94d90b24b56b..a993c108be67 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_SH_TIMER_TMU) += sh_tmu.o obj-$(CONFIG_EM_TIMER_STI) += em_sti.o obj-$(CONFIG_CLKBLD_I8253) += i8253.o obj-$(CONFIG_CLKSRC_MMIO) += mmio.o +obj-$(CONFIG_ARCH_DIGICOLOR) += timer-digicolor.o obj-$(CONFIG_DW_APB_TIMER) += dw_apb_timer.o obj-$(CONFIG_DW_APB_TIMER_OF) += dw_apb_timer_of.o obj-$(CONFIG_CLKSRC_NOMADIK_MTU) += nomadik-mtu.o diff --git a/drivers/clocksource/timer-digicolor.c b/drivers/clocksource/timer-digicolor.c new file mode 100644 index 000000000000..c97ea7eac4a5 --- /dev/null +++ b/drivers/clocksource/timer-digicolor.c @@ -0,0 +1,170 @@ +/* + * Conexant Digicolor timer driver + * + * Author: Baruch Siach + * + * Copyright (C) 2014 Paradox Innovation Ltd. + * + * Based on: + * Allwinner SoCs hstimer driver + * + * Copyright (C) 2013 Maxime Ripard + * + * Maxime Ripard + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/* + * Conexant Digicolor SoCs have 8 configurable timers, named from "Timer A" to + * "Timer H". Timer A is the only one with watchdog support, so it is dedicated + * to the watchdog driver. This driver uses Timer B for sched_clock(), and + * Timer C for clockevents. + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +enum { + TIMER_A, + TIMER_B, + TIMER_C, + TIMER_D, + TIMER_E, + TIMER_F, + TIMER_G, + TIMER_H, +}; + +#define CONTROL(t) ((t)*8) +#define COUNT(t) ((t)*8 + 4) + +#define CONTROL_DISABLE 0 +#define CONTROL_ENABLE BIT(0) +#define CONTROL_MODE(m) ((m) << 4) +#define CONTROL_MODE_ONESHOT CONTROL_MODE(1) +#define CONTROL_MODE_PERIODIC CONTROL_MODE(2) + +static struct dc_dev_t { + void __iomem *timer_base; + u32 ticks_per_jiffy; +} dc_dev; + +static void digicolor_clkevt_mode(enum clock_event_mode mode, + struct clock_event_device *clk) +{ + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + writeb(CONTROL_DISABLE, dc_dev.timer_base + CONTROL(TIMER_C)); + writel(dc_dev.ticks_per_jiffy, + dc_dev.timer_base + COUNT(TIMER_C)); + writeb(CONTROL_ENABLE | CONTROL_MODE_PERIODIC, + dc_dev.timer_base + CONTROL(TIMER_C)); + break; + case CLOCK_EVT_MODE_ONESHOT: + writeb(CONTROL_DISABLE, dc_dev.timer_base + CONTROL(TIMER_C)); + writeb(CONTROL_ENABLE | CONTROL_MODE_ONESHOT, + dc_dev.timer_base + CONTROL(TIMER_C)); + break; + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: + default: + writeb(CONTROL_DISABLE, dc_dev.timer_base + CONTROL(TIMER_C)); + break; + } +} + +static int digicolor_clkevt_next_event(unsigned long evt, + struct clock_event_device *unused) +{ + writeb(CONTROL_DISABLE, dc_dev.timer_base + CONTROL(TIMER_C)); + writel(evt, dc_dev.timer_base + COUNT(TIMER_C)); + writeb(CONTROL_ENABLE | CONTROL_MODE_ONESHOT, + dc_dev.timer_base + CONTROL(TIMER_C)); + + return 0; +} + +static struct clock_event_device digicolor_clockevent = { + .name = "digicolor_tick", + .rating = 340, + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .set_mode = digicolor_clkevt_mode, + .set_next_event = digicolor_clkevt_next_event, +}; + +static irqreturn_t digicolor_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = dev_id; + + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static u64 digicolor_timer_sched_read(void) +{ + return ~readl(dc_dev.timer_base + COUNT(TIMER_B)); +} + +static void __init digicolor_timer_init(struct device_node *node) +{ + unsigned long rate; + struct clk *clk; + int ret, irq; + + dc_dev.timer_base = + of_io_request_and_map(node, 0, of_node_full_name(node)); + if (!dc_dev.timer_base) { + pr_err("Can't map registers"); + return; + } + + irq = irq_of_parse_and_map(node, TIMER_C); + if (irq <= 0) { + pr_err("Can't parse IRQ"); + return; + } + + clk = of_clk_get(node, 0); + if (IS_ERR(clk)) { + pr_err("Can't get timer clock"); + return; + } + clk_prepare_enable(clk); + rate = clk_get_rate(clk); + dc_dev.ticks_per_jiffy = DIV_ROUND_UP(rate, HZ); + + writeb(CONTROL_DISABLE, dc_dev.timer_base + CONTROL(TIMER_B)); + writel(UINT_MAX, dc_dev.timer_base + COUNT(TIMER_B)); + writeb(CONTROL_ENABLE, dc_dev.timer_base + CONTROL(TIMER_B)); + + sched_clock_register(digicolor_timer_sched_read, 32, rate); + clocksource_mmio_init(dc_dev.timer_base + COUNT(TIMER_B), node->name, + rate, 340, 32, clocksource_mmio_readl_down); + + ret = request_irq(irq, digicolor_timer_interrupt, + IRQF_TIMER | IRQF_IRQPOLL, "digicolor_timerC", + &digicolor_clockevent); + if (ret) + pr_warn("request of timer irq %d failed (%d)\n", irq, ret); + + digicolor_clockevent.cpumask = cpu_possible_mask; + digicolor_clockevent.irq = irq; + + clockevents_config_and_register(&digicolor_clockevent, rate, 0, + 0xffffffff); +} +CLOCKSOURCE_OF_DECLARE(conexant_digicolor, "cnxt,cx92755-timer", + digicolor_timer_init);