| Message ID | d6dc41952961e5c7b21acac08a8bf1eb0f69e124.1671123115.git.robin.murphy@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | iommu/arm-smmu: Report IOMMU_CAP_CACHE_COHERENCY even betterer | expand |
On Thu, Dec 15, 2022 at 04:51:55PM +0000, Robin Murphy wrote: > Although it's vanishingly unlikely that anyone would integrate an SMMU > within a coherent interconnect without also making the pagetable walk > interface coherent, the same effect happens if a coherent SMMU fails to > advertise CTTW correctly. This turns out to be the case on some popular > NXP SoCs, where VFIO started failing the IOMMU_CAP_CACHE_COHERENCY test, > even though IOMMU_CACHE *was* previously achieving the desired effect > anyway thanks to the underlying integration. > > While those SoCs stand to gain some more general benefits from a > firmware update to override CTTW correctly in DT/ACPI, it's also easy > to work around this in Linux as well, to avoid imposing too much on > affected users - since the upstream client devices *are* correctly > marked as coherent, we can trivially infer their coherent paths through > the SMMU as well. > > Reported-by: Vladimir Oltean <vladimir.oltean@nxp.com> > Fixes: df198b37e72c ("iommu/arm-smmu: Report IOMMU_CAP_CACHE_COHERENCY better") > Signed-off-by: Robin Murphy <robin.murphy@arm.com> > --- Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com> Thanks for the help!
Hi, On Thu, Dec 15, 2022 at 04:51:55PM +0000, Robin Murphy wrote: > Although it's vanishingly unlikely that anyone would integrate an SMMU > within a coherent interconnect without also making the pagetable walk > interface coherent, the same effect happens if a coherent SMMU fails to > advertise CTTW correctly. This turns out to be the case on some popular > NXP SoCs, where VFIO started failing the IOMMU_CAP_CACHE_COHERENCY test, > even though IOMMU_CACHE *was* previously achieving the desired effect > anyway thanks to the underlying integration. > > While those SoCs stand to gain some more general benefits from a > firmware update to override CTTW correctly in DT/ACPI, it's also easy > to work around this in Linux as well, to avoid imposing too much on > affected users - since the upstream client devices *are* correctly > marked as coherent, we can trivially infer their coherent paths through > the SMMU as well. > > Reported-by: Vladimir Oltean <vladimir.oltean@nxp.com> > Fixes: df198b37e72c ("iommu/arm-smmu: Report IOMMU_CAP_CACHE_COHERENCY better") > Signed-off-by: Robin Murphy <robin.murphy@arm.com> > --- Could someone please apply this patch?
On Tue, Jan 10, 2023 at 12:56:25PM +0200, Vladimir Oltean wrote: > On Thu, Dec 15, 2022 at 04:51:55PM +0000, Robin Murphy wrote: > > Although it's vanishingly unlikely that anyone would integrate an SMMU > > within a coherent interconnect without also making the pagetable walk > > interface coherent, the same effect happens if a coherent SMMU fails to > > advertise CTTW correctly. This turns out to be the case on some popular > > NXP SoCs, where VFIO started failing the IOMMU_CAP_CACHE_COHERENCY test, > > even though IOMMU_CACHE *was* previously achieving the desired effect > > anyway thanks to the underlying integration. > > > > While those SoCs stand to gain some more general benefits from a > > firmware update to override CTTW correctly in DT/ACPI, it's also easy > > to work around this in Linux as well, to avoid imposing too much on > > affected users - since the upstream client devices *are* correctly > > marked as coherent, we can trivially infer their coherent paths through > > the SMMU as well. > > > > Reported-by: Vladimir Oltean <vladimir.oltean@nxp.com> > > Fixes: df198b37e72c ("iommu/arm-smmu: Report IOMMU_CAP_CACHE_COHERENCY better") > > Signed-off-by: Robin Murphy <robin.murphy@arm.com> > > --- > > Could someone please apply this patch? Sorry, I missed that this was fixing a recent regression. I'll pick it up today and send it to Joerg. Will
On Thu, 15 Dec 2022 16:51:55 +0000, Robin Murphy wrote: > Although it's vanishingly unlikely that anyone would integrate an SMMU > within a coherent interconnect without also making the pagetable walk > interface coherent, the same effect happens if a coherent SMMU fails to > advertise CTTW correctly. This turns out to be the case on some popular > NXP SoCs, where VFIO started failing the IOMMU_CAP_CACHE_COHERENCY test, > even though IOMMU_CACHE *was* previously achieving the desired effect > anyway thanks to the underlying integration. > > [...] Applied to will (for-joerg/arm-smmu/fixes), thanks! [1/1] iommu/arm-smmu: Report IOMMU_CAP_CACHE_COHERENCY even betterer https://git.kernel.org/will/c/259c2ec3c5f3 Cheers,
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index 30dab1418e3f..0e679ad3171f 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -1319,8 +1319,14 @@ static bool arm_smmu_capable(struct device *dev, enum iommu_cap cap) switch (cap) { case IOMMU_CAP_CACHE_COHERENCY: - /* Assume that a coherent TCU implies coherent TBUs */ - return cfg->smmu->features & ARM_SMMU_FEAT_COHERENT_WALK; + /* + * It's overwhelmingly the case in practice that when the pagetable + * walk interface is connected to a coherent interconnect, all the + * translation interfaces are too. Furthermore if the device is + * natively coherent, then its translation interface must also be. + */ + return cfg->smmu->features & ARM_SMMU_FEAT_COHERENT_WALK || + device_get_dma_attr(dev) == DEV_DMA_COHERENT; case IOMMU_CAP_NOEXEC: return true; default:
Although it's vanishingly unlikely that anyone would integrate an SMMU within a coherent interconnect without also making the pagetable walk interface coherent, the same effect happens if a coherent SMMU fails to advertise CTTW correctly. This turns out to be the case on some popular NXP SoCs, where VFIO started failing the IOMMU_CAP_CACHE_COHERENCY test, even though IOMMU_CACHE *was* previously achieving the desired effect anyway thanks to the underlying integration. While those SoCs stand to gain some more general benefits from a firmware update to override CTTW correctly in DT/ACPI, it's also easy to work around this in Linux as well, to avoid imposing too much on affected users - since the upstream client devices *are* correctly marked as coherent, we can trivially infer their coherent paths through the SMMU as well. Reported-by: Vladimir Oltean <vladimir.oltean@nxp.com> Fixes: df198b37e72c ("iommu/arm-smmu: Report IOMMU_CAP_CACHE_COHERENCY better") Signed-off-by: Robin Murphy <robin.murphy@arm.com> --- drivers/iommu/arm/arm-smmu/arm-smmu.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-)