| Message ID | da598378f733a8d45a35ed77f9626cc082262b1a.1710226514.git.andrea.porta@suse.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | dmaengine: bcm2835: add BCM2711 40-bit DMA support | expand |
Hi Andrea, Am 13.03.24 um 15:08 schrieb Andrea della Porta: > From: Phil Elwell <phil@raspberrypi.org> > > Add the ability to interpret the high bits of the dreq specifier as > flags to be included in the DMA_CS register. The motivation for this > change is the ability to set the DISDEBUG flag for SD card transfers > to avoid corruption when using the VPU debugger. AFAIK this and the following 2 patches also requires modification on the DT side. So either they must be included in the series or we better leave them out completely. I'm not sure which one are really necessary for 40 bit support. Regards > > Signed-off-by: Phil Elwell <phil@raspberrypi.org> > Signed-off-by: Andrea della Porta <andrea.porta@suse.com> > --- > drivers/dma/bcm2835-dma.c | 10 ++++++++-- > 1 file changed, 8 insertions(+), 2 deletions(-) > > diff --git a/drivers/dma/bcm2835-dma.c b/drivers/dma/bcm2835-dma.c > index 428253b468ac..3d9973dd041d 100644 > --- a/drivers/dma/bcm2835-dma.c > +++ b/drivers/dma/bcm2835-dma.c > @@ -137,6 +137,10 @@ struct bcm2835_desc { > #define BCM2835_DMA_S_DREQ BIT(10) /* enable SREQ for source */ > #define BCM2835_DMA_S_IGNORE BIT(11) /* ignore source reads - read 0 */ > #define BCM2835_DMA_BURST_LENGTH(x) (((x) & 15) << 12) > +#define BCM2835_DMA_CS_FLAGS(x) ((x) & (BCM2835_DMA_PRIORITY(15) | \ > + BCM2835_DMA_PANIC_PRIORITY(15) | \ > + BCM2835_DMA_WAIT_FOR_WRITES | \ > + BCM2835_DMA_DIS_DEBUG)) > #define BCM2835_DMA_PER_MAP(x) (((x) & 31) << 16) /* REQ source */ > #define BCM2835_DMA_WAIT(x) (((x) & 31) << 21) /* add DMA-wait cycles */ > #define BCM2835_DMA_NO_WIDE_BURSTS BIT(26) /* no 2 beat write bursts */ > @@ -449,7 +453,8 @@ static void bcm2835_dma_start_desc(struct bcm2835_chan *c) > c->desc = to_bcm2835_dma_desc(&vd->tx); > > writel(c->desc->cb_list[0].paddr, c->chan_base + BCM2835_DMA_ADDR); > - writel(BCM2835_DMA_ACTIVE, c->chan_base + BCM2835_DMA_CS); > + writel(BCM2835_DMA_ACTIVE | BCM2835_DMA_CS_FLAGS(c->dreq), > + c->chan_base + BCM2835_DMA_CS); > } > > static irqreturn_t bcm2835_dma_callback(int irq, void *data) > @@ -476,7 +481,8 @@ static irqreturn_t bcm2835_dma_callback(int irq, void *data) > * if this IRQ handler is threaded.) If the channel is finished, it > * will remain idle despite the ACTIVE flag being set. > */ > - writel(BCM2835_DMA_INT | BCM2835_DMA_ACTIVE, > + writel(BCM2835_DMA_INT | BCM2835_DMA_ACTIVE | > + BCM2835_DMA_CS_FLAGS(c->dreq), > c->chan_base + BCM2835_DMA_CS); > > d = c->desc;
diff --git a/drivers/dma/bcm2835-dma.c b/drivers/dma/bcm2835-dma.c index 428253b468ac..3d9973dd041d 100644 --- a/drivers/dma/bcm2835-dma.c +++ b/drivers/dma/bcm2835-dma.c @@ -137,6 +137,10 @@ struct bcm2835_desc { #define BCM2835_DMA_S_DREQ BIT(10) /* enable SREQ for source */ #define BCM2835_DMA_S_IGNORE BIT(11) /* ignore source reads - read 0 */ #define BCM2835_DMA_BURST_LENGTH(x) (((x) & 15) << 12) +#define BCM2835_DMA_CS_FLAGS(x) ((x) & (BCM2835_DMA_PRIORITY(15) | \ + BCM2835_DMA_PANIC_PRIORITY(15) | \ + BCM2835_DMA_WAIT_FOR_WRITES | \ + BCM2835_DMA_DIS_DEBUG)) #define BCM2835_DMA_PER_MAP(x) (((x) & 31) << 16) /* REQ source */ #define BCM2835_DMA_WAIT(x) (((x) & 31) << 21) /* add DMA-wait cycles */ #define BCM2835_DMA_NO_WIDE_BURSTS BIT(26) /* no 2 beat write bursts */ @@ -449,7 +453,8 @@ static void bcm2835_dma_start_desc(struct bcm2835_chan *c) c->desc = to_bcm2835_dma_desc(&vd->tx); writel(c->desc->cb_list[0].paddr, c->chan_base + BCM2835_DMA_ADDR); - writel(BCM2835_DMA_ACTIVE, c->chan_base + BCM2835_DMA_CS); + writel(BCM2835_DMA_ACTIVE | BCM2835_DMA_CS_FLAGS(c->dreq), + c->chan_base + BCM2835_DMA_CS); } static irqreturn_t bcm2835_dma_callback(int irq, void *data) @@ -476,7 +481,8 @@ static irqreturn_t bcm2835_dma_callback(int irq, void *data) * if this IRQ handler is threaded.) If the channel is finished, it * will remain idle despite the ACTIVE flag being set. */ - writel(BCM2835_DMA_INT | BCM2835_DMA_ACTIVE, + writel(BCM2835_DMA_INT | BCM2835_DMA_ACTIVE | + BCM2835_DMA_CS_FLAGS(c->dreq), c->chan_base + BCM2835_DMA_CS); d = c->desc;