From patchwork Mon Sep 9 17:03:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jan Kiszka X-Patchwork-Id: 13797328 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D3842ECE579 for ; Mon, 9 Sep 2024 17:07:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc: To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=pbaSHR6gWwTrDpVu1u28lrL5fvBdgrwbK17O8dh9Nb8=; b=MriTNvmYqmwgoMh+idYZZz5LOO DJTp7ZEHoxHzdLK9Ux6DaPxs4PrvnKOW+Wnw5q1VDbY+rtoY/1+XF6Y46cE4ep6ccn/r74OrUhtzo YI5tu61jW5hh3mEXhOu5wEQBy78z3NFyIs8MMmI/pikNQxiB5qKZe106E7m/G88CgUUSp//xZCsrj AwrdxF0ykr6y0Pg2tC/i4mwpPKBeyKSXYq2shANpm8+xMlgVZN8uhpjIZUowIJBPNadxEp4DDBheH GLAShK4Sv3ZL/rMHNQQVWvyEw8Qy7WC3a0ZgHNiCQRX2n66khB3xNwkRe97rQNWI0bZlo7g8UOnBX FXyQdLqA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1snhrP-00000002lOP-1ENr; Mon, 09 Sep 2024 17:07:31 +0000 Received: from mta-64-227.siemens.flowmailer.net ([185.136.64.227]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1snho6-00000002kO8-2T5m for linux-arm-kernel@lists.infradead.org; Mon, 09 Sep 2024 17:04:10 +0000 Received: by mta-64-227.siemens.flowmailer.net with ESMTPSA id 202409091704029393d2a103b151316c for ; Mon, 09 Sep 2024 19:04:02 +0200 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=fm1; d=siemens.com; i=jan.kiszka@siemens.com; h=Date:From:Subject:To:Message-ID:MIME-Version:Content-Type:Content-Transfer-Encoding:Cc:References:In-Reply-To; bh=pbaSHR6gWwTrDpVu1u28lrL5fvBdgrwbK17O8dh9Nb8=; b=ScQK1RKbdCkAnyYYvwnpBUWq3I03gaXAZQ1LnO72cjzrbhWM1icAG0ssrzOFI2hPldh8wT yyHokP7FKSzX9vk5BLIJb70Hwq/6g209uoPuT6+NtodNEYk5XQCi4AJqoM+V2/6F53GfXFzC YrzSYSAE9saU/xW/iiEbFmNmsg12WTMD9lfj/p9HgEFMTGMIMji66+UsB+185vS3kv8ym8WI GAw4WfQ9vBTZ9uCcPMzNdhhzIocqMLh78L8hEbyjJNAkUKWISgRzhYbBu+qSDMwdj1dxbfaZ NJrpO7g6KhjsD0HGZtciwS6v4/sgZw76/BZPl0zHaE9ZsO0sBRgTKqoQ==; From: Jan Kiszka To: Nishanth Menon , Santosh Shilimkar , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, Siddharth Vadapalli , Bao Cheng Su , Hua Qian Li , Diogo Ivo , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas Subject: [PATCH v6 2/7] dt-bindings: PCI: ti,am65: Extend for use with PVU Date: Mon, 9 Sep 2024 19:03:55 +0200 Message-ID: In-Reply-To: References: MIME-Version: 1.0 X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-294854:519-21489:flowmailer X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240909_100407_171099_5630978D X-CRM114-Status: GOOD ( 13.49 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Jan Kiszka The PVU on the AM65 SoC is capable of restricting DMA from PCIe devices to specific regions of host memory. Add the optional property "memory-regions" to point to such regions of memory when PVU is used. Since the PVU deals with system physical addresses, utilizing the PVU with PCIe devices also requires setting up the VMAP registers to map the Requester ID of the PCIe device to the CBA Virtual ID, which in turn is mapped to the system physical address. Hence, describe the VMAP registers which are optional unless the PVU shall be used for PCIe. Signed-off-by: Jan Kiszka Reviewed-by: Krzysztof Kozlowski --- CC: Lorenzo Pieralisi CC: "Krzysztof Wilczyński" CC: Bjorn Helgaas CC: linux-pci@vger.kernel.org --- .../bindings/pci/ti,am65-pci-host.yaml | 28 +++++++++++++++++-- 1 file changed, 25 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml index 0a9d10532cc8..98f6c7f1b1a6 100644 --- a/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml @@ -20,14 +20,18 @@ properties: - ti,keystone-pcie reg: - maxItems: 4 + minItems: 4 + maxItems: 6 reg-names: + minItems: 4 items: - const: app - const: dbics - const: config - const: atu + - const: vmap_lp + - const: vmap_hp interrupts: maxItems: 1 @@ -69,6 +73,15 @@ properties: items: pattern: '^pcie-phy[0-1]$' + memory-region: + maxItems: 1 + description: | + phandle to a restricted DMA pool to be used for all devices behind + this controller. The regions should be defined according to + reserved-memory/shared-dma-pool.yaml. + Note that enforcement via the PVU will only be available to + ti,am654-pcie-rc devices. + required: - compatible - reg @@ -89,6 +102,13 @@ then: - power-domains - msi-map - num-viewport +else: + properties: + reg: + maxItems: 4 + + reg-names: + maxItems: 4 unevaluatedProperties: false @@ -104,8 +124,10 @@ examples: reg = <0x5500000 0x1000>, <0x5501000 0x1000>, <0x10000000 0x2000>, - <0x5506000 0x1000>; - reg-names = "app", "dbics", "config", "atu"; + <0x5506000 0x1000>, + <0x2900000 0x1000>, + <0x2908000 0x1000>; + reg-names = "app", "dbics", "config", "atu", "vmap_lp", "vmap_hp"; power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; #address-cells = <3>; #size-cells = <2>;