From patchwork Wed Jul 12 16:39:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mason X-Patchwork-Id: 9837155 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 85642602D8 for ; Wed, 12 Jul 2017 16:40:16 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 74E31285C1 for ; Wed, 12 Jul 2017 16:40:16 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 68ED228645; Wed, 12 Jul 2017 16:40:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,FREEMAIL_FROM autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A9F04285FD for ; Wed, 12 Jul 2017 16:40:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date: Message-ID:References:To:From:Subject:Reply-To:Content-ID:Content-Description :Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=xcfB9clqjVM5/LIOzJoWbT2jqE/GYN2u5zj038sPBWw=; b=gg2y/xgG+/GkkN biPLbEw/wKo5A6jGssP/ieqhn0YxGCkZ1RtLBMWcctUw8GYpvo9y0V0Am3deM6ZcxrLIz2jqDWs0Z NRQ9/u8PfyWSUEt6Ib1Q3HDYD5NToswq882XTqA0cszzGYOCkIgCBkwXvFgyPUTLG+0trUSWJxcEP 4nHVLHFQC86MHkPdc+oG/5Lwxn5TfmOQ/FtkK3/8C/SzLWXIhObpYBxtWfaxwuBm1JQpmAb8lceho A0R2pu8irov6jpu6Uv8R41+6bM1qPBg+D6zBYnGvrrxWXB8iSbVk2gr6sXSywJLaam1SW2nl6LXFF sYEVc8hcdZTFa+zwN4Bw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1dVKgQ-00085B-5c; Wed, 12 Jul 2017 16:40:14 +0000 Received: from smtp5-g21.free.fr ([2a01:e0c:1:1599::14]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1dVKgM-0006GO-0D for linux-arm-kernel@lists.infradead.org; Wed, 12 Jul 2017 16:40:12 +0000 Received: from [172.27.0.114] (unknown [92.154.11.170]) (Authenticated sender: slash.tmp) by smtp5-g21.free.fr (Postfix) with ESMTPSA id 3014E5FFA2; Wed, 12 Jul 2017 18:39:28 +0200 (CEST) Subject: [RFC PATCH v2] irqchip: Add support for tango interrupt router From: Mason To: Marc Zyngier References: <657580dd-0cfe-e377-e425-0deabf6d20c3@free.fr> <20170606175219.34ef62b9@free-electrons.com> Message-ID: Date: Wed, 12 Jul 2017 18:39:27 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Firefox/52.0 SeaMonkey/2.49.1 MIME-Version: 1.0 In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170712_094010_375763_435B49B4 X-CRM114-Status: GOOD ( 21.46 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Petazzoni , Mark Rutland , Jason Cooper , Thibaud Cornic , LKML , Thomas Gleixner , Linux ARM Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP 128 inputs, 24 outputs (to GIC SPI 0-23) --- There might be a few things wrong with this driver. When I cat /proc/interrupts the interrupt count appears to be bogus (as if level IRQ counts are added to edge IRQ counts). Did I mess something up with the IRQ domains? --- .../interrupt-controller/sigma,smp8759-intc.txt | 18 ++ drivers/irqchip/Makefile | 2 +- drivers/irqchip/irq-smp8759.c | 203 +++++++++++++++++++++ 3 files changed, 222 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sigma,smp8759-intc.txt create mode 100644 drivers/irqchip/irq-smp8759.c diff --git a/Documentation/devicetree/bindings/interrupt-controller/sigma,smp8759-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/sigma,smp8759-intc.txt new file mode 100644 index 000000000000..9ec922f3c0a4 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/sigma,smp8759-intc.txt @@ -0,0 +1,18 @@ +Sigma Designs SMP8759 interrupt router + +Required properties: +- compatible: "sigma,smp8759-intc" +- reg: address/size of register area +- interrupt-controller +- #interrupt-cells: <2> (hwirq and trigger_type) +- interrupt-parent: parent phandle + +Example: + + interrupt-controller@6f800 { + compatible = "sigma,smp8759-intc"; + reg = <0x6f800 0x430>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + }; diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index e4dbfc85abdb..013104923b71 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -47,7 +47,7 @@ obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o obj-$(CONFIG_ARCH_NSPIRE) += irq-zevio.o obj-$(CONFIG_ARCH_VT8500) += irq-vt8500.o obj-$(CONFIG_ST_IRQCHIP) += irq-st.o -obj-$(CONFIG_TANGO_IRQ) += irq-tango.o +obj-$(CONFIG_TANGO_IRQ) += irq-tango.o irq-smp8759.o obj-$(CONFIG_TB10X_IRQC) += irq-tb10x.o obj-$(CONFIG_TS4800_IRQ) += irq-ts4800.o obj-$(CONFIG_XTENSA) += irq-xtensa-pic.o diff --git a/drivers/irqchip/irq-smp8759.c b/drivers/irqchip/irq-smp8759.c new file mode 100644 index 000000000000..ec7fee4574ef --- /dev/null +++ b/drivers/irqchip/irq-smp8759.c @@ -0,0 +1,203 @@ +#include +#include +#include +#include + +#define IRQ_MAX 128 +#define SPI_MAX 24 /* 24 output lines routed to SPI 0-23 */ +#define LEVEL_SPI 17 +#define IRQ_ENABLE BIT(31) + +/* + * 128 inputs mapped to 24 outputs + * LEVEL_HIGH IRQs are muxed on output line 'LEVEL_SPI' + * EDGE_RISING IRQs get a dedicated output line + * gic_spi_to_tango_hwirq array maps GIC SPI hwirq to tango hwirq + */ +struct tango_intc { + DECLARE_BITMAP(enabled, IRQ_MAX); + spinlock_t lock; + void __iomem *config; + void __iomem *status; + struct irq_domain *dom; + u8 gic_spi_to_tango_hwirq[SPI_MAX]; +}; + +static void tango_level_isr(struct irq_desc *desc) +{ + unsigned int pos, virq; + struct irq_chip *chip = irq_desc_get_chip(desc); + struct tango_intc *intc = irq_desc_get_handler_data(desc); + DECLARE_BITMAP(status, IRQ_MAX); + + chained_irq_enter(chip, desc); + + memcpy_fromio(status, intc->status, IRQ_MAX / BITS_PER_BYTE); + spin_lock(&intc->lock); + bitmap_and(status, status, intc->enabled, IRQ_MAX); + spin_unlock(&intc->lock); + for_each_set_bit(pos, status, IRQ_MAX) { + virq = irq_find_mapping(intc->dom, pos); + generic_handle_irq(virq); + } + + chained_irq_exit(chip, desc); +} + +static void tango_edge_isr(struct irq_desc *desc) +{ + unsigned int virq; + struct irq_data *d = &desc->irq_data; + struct irq_chip *chip = irq_desc_get_chip(desc); + struct tango_intc *intc = irq_desc_get_handler_data(desc); + + /* I don't know how to get the SPI number, d->hwirq - 32 is a hack */ + int hwirq = intc->gic_spi_to_tango_hwirq[d->hwirq - 32]; + //printk("%s: SPI=%lu hwirq=%d\n", __func__, d->hwirq, hwirq); + + chained_irq_enter(chip, desc); + virq = irq_find_mapping(intc->dom, hwirq); + generic_handle_irq(virq); + chained_irq_exit(chip, desc); +} + +static void tango_mask(struct irq_data *data) +{ + unsigned long flags; + struct tango_intc *intc = data->chip_data; + + spin_lock_irqsave(&intc->lock, flags); + __clear_bit(data->hwirq, intc->enabled); + writel_relaxed(0, intc->config + data->hwirq * 4); + spin_unlock_irqrestore(&intc->lock, flags); +} + +static void tango_unmask(struct irq_data *data) +{ + unsigned long flags; + struct tango_intc *intc = data->chip_data; + +#if 0 + if (!in_irq() && !in_interrupt()) { + printk("HWIRQ=%lu mask=%u\n", data->hwirq, data->mask); + dump_stack(); + } +#endif + + spin_lock_irqsave(&intc->lock, flags); + __set_bit(data->hwirq, intc->enabled); + writel_relaxed(IRQ_ENABLE | data->mask, intc->config + data->hwirq * 4); + spin_unlock_irqrestore(&intc->lock, flags); +} + +static int find_free_output_line(struct tango_intc *intc) +{ + int spi; + + for (spi = 0; spi < SPI_MAX; ++spi) + if (intc->gic_spi_to_tango_hwirq[spi] == 0) + return spi; + + return -ENOSPC; +} + +int tango_set_type(struct irq_data *data, unsigned int flow_type) +{ + struct tango_intc *intc = data->chip_data; + printk("%s: IRQ=%lu type=%x\n", __func__, data->hwirq, flow_type); + dump_stack(); + if (flow_type & IRQ_TYPE_LEVEL_HIGH) { + data->mask = LEVEL_SPI; + return 0; + } + + if (flow_type & IRQ_TYPE_EDGE_RISING) { + int res = find_free_output_line(intc); + if (res < 0) + return res; + data->mask = res; + intc->gic_spi_to_tango_hwirq[res] = data->hwirq; + printk("Map tango hwirq %lu to GIC SPI %d\n", data->hwirq, res); + return 0; + } + + /* LEVEL_LOW and EDGE_FALLING are not supported */ + return -ENOSYS; +} + +static struct irq_chip tango_chip = { + .name = "tango", + .irq_mask = tango_mask, + .irq_unmask = tango_unmask, + .irq_set_type = tango_set_type, +}; + +static int tango_map(struct irq_domain *dom, unsigned int virq, irq_hw_number_t hw) +{ + struct tango_intc *intc = dom->host_data; + struct irq_desc *desc = irq_to_desc(virq); + printk("%s: dom=%p virq=%u hwirq=%lu desc=%p\n", __func__, dom, virq, hw, desc); + irq_domain_set_info(dom, virq, hw, &tango_chip, intc, handle_simple_irq, NULL, NULL); + return 0; +} + +static void tango_unmap(struct irq_domain *d, unsigned int virq) +{ + printk("%s: dom=%p virq=%u\n", __func__, d, virq); + dump_stack(); +} + +struct irq_domain_ops dom_ops = +{ + .map = tango_map, + .unmap = tango_unmap, + .xlate = irq_domain_xlate_twocell, +}; + +#include + +static int __init map_irq(struct device_node *gic, int irq, int type) +{ + struct of_phandle_args irq_data = { gic, 3, { GIC_SPI, irq, type }}; + return irq_create_of_mapping(&irq_data); +} + +static int __init tango_irq_init(struct device_node *node, struct device_node *parent) +{ + int spi, virq; + struct irq_domain *irq_dom; + void __iomem *base; + struct tango_intc *intc = kzalloc(sizeof(*intc), GFP_KERNEL); + + base = of_iomap(node, 0); + if (!base) + panic("%s: of_iomap failed", node->name); + + virq = map_irq(parent, LEVEL_SPI, IRQ_TYPE_LEVEL_HIGH); + if (!virq) + panic("%s: Failed to map IRQ %d\n", node->name, LEVEL_SPI); + + irq_set_chained_handler_and_data(virq, tango_level_isr, intc); + + for (spi = 0; spi < SPI_MAX; ++spi) { + if (spi == LEVEL_SPI) + continue; + + virq = map_irq(parent, spi, IRQ_TYPE_EDGE_RISING); + if (!virq) + panic("%s: Failed to map IRQ %d\n", node->name, spi); + + irq_set_chained_handler_and_data(virq, tango_edge_isr, intc); + } + + irq_dom = irq_domain_add_linear(node, IRQ_MAX, &dom_ops, intc); + + spin_lock_init(&intc->lock); + intc->config = base; + intc->status = base + 0x420; + intc->dom = irq_dom; + intc->gic_spi_to_tango_hwirq[LEVEL_SPI] = ~0; + + return 0; +} +IRQCHIP_DECLARE(tango_intc, "sigma,smp8759-intc", tango_irq_init);