diff mbox series

[6/6] arm64: dts: Add SMMU PMUs to Juno

Message ID e33aa6738926a1d2b9cd508c7b16ebbb6994d5b5.1645106346.git.robin.murphy@arm.com (mailing list archive)
State New, archived
Headers show
Series perf: Arm SMMU PMU driver | expand

Commit Message

Robin Murphy Feb. 17, 2022, 2:24 p.m. UTC 
MMU-401 implements a single counter group, with correspondingly a
single overflow interrupt, which is also muxed into the combined
interrupt output; the integrations in Juno rely on the latter.

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
 arch/arm64/boot/dts/arm/juno-base.dtsi | 26 ++++++++++++++++++++------
 1 file changed, 20 insertions(+), 6 deletions(-)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
index 6288e104a089..9e242ea84871 100644
--- a/arch/arm64/boot/dts/arm/juno-base.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
@@ -48,20 +48,25 @@  smmu_pcie: iommu@2b500000 {
 		compatible = "arm,mmu-401", "arm,smmu-v1";
 		reg = <0x0 0x2b500000 0x0 0x10000>;
 		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 		#iommu-cells = <1>;
-		#global-interrupts = <1>;
+		#global-interrupts = <2>;
+		#pmu-interrupts = <1>;
 		dma-coherent;
 		status = "disabled";
+
 	};
 
 	smmu_etr: iommu@2b600000 {
 		compatible = "arm,mmu-401", "arm,smmu-v1";
 		reg = <0x0 0x2b600000 0x0 0x10000>;
 		interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 		#iommu-cells = <1>;
-		#global-interrupts = <1>;
+		#global-interrupts = <2>;
+		#pmu-interrupts = <1>;
 		dma-coherent;
 		power-domains = <&scpi_devpd 0>;
 	};
@@ -638,9 +643,11 @@  smmu_dma: iommu@7fb00000 {
 		compatible = "arm,mmu-401", "arm,smmu-v1";
 		reg = <0x0 0x7fb00000 0x0 0x10000>;
 		interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 		#iommu-cells = <1>;
-		#global-interrupts = <1>;
+		#global-interrupts = <2>;
+		#pmu-interrupts = <1>;
 		dma-coherent;
 	};
 
@@ -648,27 +655,34 @@  smmu_hdlcd1: iommu@7fb10000 {
 		compatible = "arm,mmu-401", "arm,smmu-v1";
 		reg = <0x0 0x7fb10000 0x0 0x10000>;
 		interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 		#iommu-cells = <1>;
-		#global-interrupts = <1>;
+		#global-interrupts = <2>;
+		#pmu-interrupts = <1>;
+
 	};
 
 	smmu_hdlcd0: iommu@7fb20000 {
 		compatible = "arm,mmu-401", "arm,smmu-v1";
 		reg = <0x0 0x7fb20000 0x0 0x10000>;
 		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 		#iommu-cells = <1>;
-		#global-interrupts = <1>;
+		#global-interrupts = <2>;
+		#pmu-interrupts = <1>;
 	};
 
 	smmu_usb: iommu@7fb30000 {
 		compatible = "arm,mmu-401", "arm,smmu-v1";
 		reg = <0x0 0x7fb30000 0x0 0x10000>;
 		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 		#iommu-cells = <1>;
-		#global-interrupts = <1>;
+		#global-interrupts = <2>;
+		#pmu-interrupts = <1>;
 		dma-coherent;
 	};